Rafael Ruiz-Sautua

2009
12	EE	María C. Molina, Rafael Ruiz-Sautua, Pedro Garcia-Repetto, Román Hermida: Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications. IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 60-73 (2009)
2007
11	EE	María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida: Area optimization of multi-cycle operators in high-level synthesis. DATE 2007: 449-454
10	EE	Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida: Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis CoRR abs/0710.4801: (2007)
9	EE	Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias: Exploiting Bit-Level Delay Calculations to Soften Read-After-Write Dependences in Behavioral Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1589-1601 (2007)
2006
8	EE	Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida: Pre-synthesis optimization of multiplications to improve circuit performance. DATE 2006: 1306-1311
7	EE	María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida: Bitwise scheduling to balance the computational cost of behavioral specifications. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 31-46 (2006)
2005
6	EE	Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida: Arrival time aware scheduling to minimize clock cycle length. ASP-DAC 2005: 1018-1021
5	EE	Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida: Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. DATE 2005: 1252-1257
4		Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias, Román Hermida: Performance-driven read-after-write dependencies softening in high-level synthesis. ICCAD 2005: 7-12
2004
3	EE	María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida: Behavioural Bitwise Scheduling Based on Computational Effort Balancing. DATE 2004: 684-685
2	EE	María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida: Behavioural Scheduling to Balance the Bit-Level Computational Effort. ISVLSI 2004: 99-104
2003
1	EE	María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida: Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. PATMOS 2003: 617-627

Coauthor Index

1	Pedro Garcia-Repetto	[12]
2	Román Hermida	[1] [2] [3] [4] [5] [6] [7] [8] [10] [11] [12]
3	Jose Manuel Mendias (José M. Mendías)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
4	María C. Molina	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]