Mario R. Casu

2009
21	EE	Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni: A mixed-signal demodulator for a low-complexity IR-UWB receiver: Methodology, simulation and design. Integration 42(1): 47-60 (2009)
2007
20	EE	Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni: An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip. DATE 2007: 1424-1429
19	EE	Mario R. Casu, Luca Macchiarulo: Adaptive Latency-Insensitive Protocols. IEEE Design & Test of Computers 24(5): 442-452 (2007)
2006
18	EE	Sergio Tota, Mario R. Casu, Luca Macchiarulo: Implementation analysis of NoC: a MPSoC trace-driven approach. ACM Great Lakes Symposium on VLSI 2006: 204-209
17	EE	Mario R. Casu, Luca Macchiarulo: Floorplanning With Wire Pipelining in Adaptive Communication Channels. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2996-3004 (2006)
2005
16	EE	Mario R. Casu, Luca Macchiarulo: A New System Design Methodology for Wire Pipelined SoC. DATE 2005: 944-945
15	EE	Mario R. Casu, Luca Macchiarulo: Floorplan assisted data rate enhancement through wire pipelining: a real assessment. ISPD 2005: 121-128
14	EE	Mario R. Casu, Luca Macchiarulo: Throughput-driven floorplanning with wire pipelining. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 663-675 (2005)
13	EE	Mario R. Casu, Giuseppe Durisi: Implementation aspects of a transmitted-reference UWB receiver. Wireless Communications and Mobile Computing 5(5): 537-549 (2005)
2004
12	EE	Mario R. Casu, Luca Macchiarulo: A new approach to latency insensitive design. DAC 2004: 576-581
11	EE	Mario R. Casu, Luca Macchiarulo: Issues in Implementing Latency Insensitive Protocols. DATE 2004: 1390-1391
10	EE	Mario R. Casu, Luca Macchiarulo: On-Chip Transparent Wire Pipelining. ICCD 2004: 160-167
9	EE	Mario R. Casu, Luca Macchiarulo: Floorplanning for throughput. ISPD 2004: 62-69
8		Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: An electromigration and thermal model of power wires for a priori high-level reliability prediction. IEEE Trans. VLSI Syst. 12(4): 349-358 (2004)
7	EE	Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: Effects of temperature in deep-submicron global interconnect optimization in future technology nodes. Microelectronics Journal 35(10): 849-857 (2004)
2003
6	EE	M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. PATMOS 2003: 121-130
5	EE	Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni: Effects of Temperature in Deep-Submicron Global Interconnect Optimization. PATMOS 2003: 90-100
4	EE	Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni: Coupled electro-thermal modeling and optimization of clock networks. Microelectronics Journal 34(12): 1175-1185 (2003)
2002
3	EE	Mario R. Casu, Philippe Flatresse: Converting an Embedded Low-Power SRAM from Bulk to PD-SOI. MTDT 2002: 163-167
2	EE	Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni: Clock Distribution Network Optimization under Self-Heating and Timing Constraints. PATMOS 2002: 198-208
2001
1	EE	Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni: Synthesis of low-leakage PD-SOI circuits with body-biasing. ISLPED 2001: 287-290

Coauthor Index

1	M. Addino	[6]
2	Marco Crepaldi	[20] [21]
3	Giuseppe Durisi	[13]
4	Philippe Flatresse	[3]
5	Mariagrazia Graziano (M. Graziano)	[2] [4] [5] [7] [8] [20] [21]
6	Luca Macchiarulo	[9] [10] [11] [12] [14] [15] [16] [17] [18] [19]
7	Guido Masera	[1] [2] [4] [5] [6] [7] [8]
8	Gianluca Piccinini	[1] [2] [4] [5] [6] [7] [8]
9	M. M. Prono	[2]
10	Sergio Tota	[18]
11	Maurizio Zamboni	[1] [2] [4] [5] [6] [7] [8] [20] [21]

Colors in the list of coauthors