2009 |
10 | EE | Arnab Sinha,
Pallab Dasgupta,
Bhaskar Pal,
Sayantan Das,
Prasenjit Basu,
P. P. Chakrabarti:
Design intent coverage revisited.
ACM Trans. Design Autom. Electr. Syst. 14(1): (2009) |
2006 |
9 | EE | Prasenjit Basu,
Sayantan Das,
Pallab Dasgupta,
Partha Pratim Chakrabarti:
Discovering the input assumptions in specification refinement coverage.
ASP-DAC 2006: 13-18 |
8 | EE | Sayantan Das,
Prasenjit Basu,
Pallab Dasgupta,
P. P. Chakrabarti:
What lies between design intent coverage and model checking?
DATE 2006: 1217-1222 |
7 | EE | Prasenjit Basu,
Sayantan Das,
Ansuman Banerjee,
Pallab Dasgupta,
P. P. Chakrabarti,
Chunduri Rama Mohan,
Limor Fix,
Roy Armoni:
Design-Intent Coverage - A New Paradigm for Formal Property Verification.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 1922-1934 (2006) |
2005 |
6 | | Suchismita Roy,
Sayantan Das,
Prasenjit Basu,
Pallab Dasgupta,
Partha Pratim Chakrabarti:
SAT based solutions for consistency problems in formal property specifications for open systems.
ICCAD 2005: 885-888 |
5 | EE | Sayantan Das,
Ansuman Banerjee,
Prasenjit Basu,
Pallab Dasgupta,
P. P. Chakrabarti,
Chunduri Rama Mohan,
Limor Fix:
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model.
VLSI Design 2005: 201-206 |
4 | EE | Prasenjit Basu,
Pallab Dasgupta,
P. P. Chakrabarti:
Syntactic Transformation of Assume-Guarantee Assertions: From Sub-Modules to Modules.
VLSI Design 2005: 213-218 |
2004 |
3 | EE | Prasenjit Basu,
Sayantan Das,
Pallab Dasgupta,
P. P. Chakrabarti,
Chunduri Rama Mohan,
Limor Fix:
Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent?
DATE 2004: 668-669 |
2 | EE | Sayantan Das,
Prasenjit Basu,
Ansuman Banerjee,
Pallab Dasgupta,
P. P. Chakrabarti,
Chunduri Rama Mohan,
Limor Fix,
Roy Armoni:
Formal verification coverage: computing the coverage gap between temporal specifications.
ICCAD 2004: 198-203 |
1 | EE | Prasenjit Basu,
Pallab Dasgupta,
P. P. Chakrabarti,
Chunduri Rama Mohan:
Property Refinement Techniques for Enhancing Coverage of Formal Property Verification.
VLSI Design 2004: 109-114 |