| 2008 |
|---|
| 81 | EE | Lihong Zhang,
C.-J. Richard Shi,
Yingtao Jiang:
Symmetry-aware placement with transitive closure graphs for analog layout design.
ASP-DAC 2008: 180-185 |
| 80 | EE | Cherry Wakayama,
Wolf Kohn,
Zelda B. Zabinsky,
C.-J. Richard Shi:
A quantum-dot light-harvesting architecture using deterministic phase control.
ISCAS 2008: 332-335 |
| 79 | EE | Yu-Te Liao,
C.-J. Richard Shi:
A 6-11GHz multi-phase VCO design with active inductors.
ISCAS 2008: 988-991 |
| 78 | EE | Lihong Zhang,
Nuttorn Jangkrajarng,
Sambuddha Bhattacharya,
C.-J. Richard Shi:
Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 791-802 (2008) |
| 77 | EE | Bo Hu,
C.-J. Richard Shi:
Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 883-892 (2008) |
| 2007 |
|---|
| 76 | EE | Guoyong Shi,
Weiwei Chen,
C.-J. Richard Shi:
A Graph Reduction Approach to Symbolic Circuit Analysis.
ASP-DAC 2007: 197-202 |
| 75 | EE | Lili Zhou,
Cherry Wakayama,
Robin Panda,
Nuttorn Jangkrajarng,
Bo Hu,
C.-J. Richard Shi:
Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits.
ICCD 2007: 194-201 |
| 74 | EE | Ming Su,
Lili Zhou,
C.-J. Richard Shi:
Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining.
ICCD 2007: 636-643 |
| 73 | EE | Lili Zhou,
Cherry Wakayama,
C.-J. Richard Shi:
CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1270-1282 (2007) |
| 72 | EE | Pavel V. Nikitin,
C.-J. Richard Shi:
VHDL-AMS based modeling and simulation of mixed-technology microsystems: a tutorial.
Integration 40(3): 261-273 (2007) |
| 2006 |
|---|
| 71 | EE | Zhao Li,
C.-J. Richard Shi:
A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings.
ASP-DAC 2006: 402-407 |
| 70 | EE | Lili Zhou,
Cherry Wakayama,
Nuttorn Jangkrajarng,
Bo Hu,
C.-J. Richard Shi:
A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits.
ASP-DAC 2006: 92-93 |
| 69 | EE | Nuttorn Jangkrajarng,
Lihong Zhang,
Sambuddha Bhattacharya,
Nathan Kohagen,
C.-J. Richard Shi:
Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts.
ICCAD 2006: 342-348 |
| 68 | EE | Bo Hu,
C.-J. Richard Shi:
Improved automatic differentiation method for efficient model compiler.
ISCAS 2006 |
| 67 | EE | Zhao Li,
C.-J. Richard Shi:
A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits With Strong Parasitic Couplings.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2868-2881 (2006) |
| 66 | EE | Zhao Li,
C.-J. Richard Shi:
SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1087-1103 (2006) |
| 65 | EE | Sambuddha Bhattacharya,
Nuttorn Jangkrajarng,
C.-J. Richard Shi:
Multilevel symmetry-constraint generation for retargeting large analog layouts.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 945-960 (2006) |
| 64 | EE | Guoyong Shi,
Bo Hu,
C.-J. Richard Shi:
On symbolic model order reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1257-1272 (2006) |
| 63 | EE | C.-J. Richard Shi,
Michael W. Tian,
Guoyong Shi:
Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1392-1400 (2006) |
| 62 | EE | Lei Yang,
C.-J. Richard Shi:
FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits.
Integration 39(4): 311-339 (2006) |
| 2005 |
|---|
| 61 | EE | Lei Yang,
Cherry Wakayama,
C.-J. Richard Shi:
Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer.
ACM Great Lakes Symposium on VLSI 2005: 138-142 |
| 60 | EE | Lei Yang,
Manyuan Shen,
Hui Liu,
C.-J. Richard Shi:
An FPGA implementation of low-density parity-check code decoder with multi-rate capability.
ASP-DAC 2005: 760-763 |
| 59 | EE | Sambuddha Bhattacharya,
Nuttorn Jangkrajarng,
C.-J. Richard Shi:
Template-driven parasitic-aware optimization of analog integrated circuit layouts.
DAC 2005: 644-647 |
| 58 | EE | Zhao Li,
C.-J. Richard Shi:
An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation.
DATE 2005: 752-757 |
| 57 | | Bo Hu,
C.-J. Richard Shi:
Fast-yet-accurate PVT simulation by combined direct and iterative methods.
ICCAD 2005: 495-501 |
| 56 | EE | Bo Hu,
Zhao Li,
Lili Zhou,
C.-J. Richard Shi,
Kwang-Hyun Baek,
Myung-Jun Choe:
Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC.
ISCAS (6) 2005: 5621-5624 |
| 55 | EE | Vikram Jandhyala,
Yasuo Kuga,
David J. Allstot,
C.-J. Richard Shi:
Bridging Circuits and Electromagnetics in a Curriculum Aimed at Microelectronic Analog and Microwave Simulation and Design.
MSE 2005: 45-46 |
| 54 | EE | Roy Hartono,
Nuttorn Jangkrajarng,
Sambuddha Bhattacharya,
C.-J. Richard Shi:
Automatic Device Layout Generation for Analog Layout Retargeting.
VLSI Design 2005: 457-462 |
| 2004 |
|---|
| 53 | EE | Zhao Li,
Ravikanth Suravarapu,
Roy Hartono,
Sambuddha Bhattacharya,
Kartikeya Mayaram,
C.-J. Richard Shi:
CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects.
ASP-DAC 2004: 163-168 |
| 52 | EE | Nuttorn Jangkrajarng,
Sambuddha Bhattacharya,
Roy Hartono,
C.-J. Richard Shi:
Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting.
ASP-DAC 2004: 394-399 |
| 51 | EE | Sambuddha Bhattacharya,
Nuttorn Jangkrajarng,
Roy Hartono,
C.-J. Richard Shi:
Hierarchical extraction and verification of symmetry constraints for analog layout automation.
ASP-DAC 2004: 400-405 |
| 50 | EE | Guoyong Shi,
C.-J. Richard Shi:
Parametric reduced order modeling for interconnect analysis.
ASP-DAC 2004: 774-779 |
| 49 | EE | Sambuddha Bhattacharya,
Nuttorn Jangkrajarng,
Roy Hartono,
C.-J. Richard Shi:
Correct-by-construction layout-centric retargeting of large analog designs.
DAC 2004: 139-144 |
| 48 | EE | Bo Wan,
C.-J. Richard Shi:
Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation.
DATE 2004: 1310-1315 |
| 47 | | Zhao Li,
C.-J. Richard Shi:
A coupled iterative/direct method for efficient time-domain simulation of nonlinear circuits with power/ground networks.
ISCAS (5) 2004: 165-168 |
| 46 | EE | Pavel V. Nikitin,
Vikram Jandhyala,
Daniel White,
Nathan Champagne,
John D. Rockway,
C.-J. Richard Shi,
Chuanyi Yang,
Yong Wang,
Gong Ouyang,
Rob Sharpe,
John W. Rockway:
Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow.
ISQED 2004: 244-249 |
| 45 | EE | Sheldon X.-D. Tan,
C.-J. Richard Shi:
Efficient approximation of symbolic expressions for analog behavioral modeling and analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 907-918 (2004) |
| 2003 |
|---|
| 44 | EE | Alicia Manthe,
Zhao Li,
C.-J. Richard Shi:
Symbolic analysis of analog circuits with hard nonlinearity.
DAC 2003: 542-545 |
| 43 | EE | Alicia Manthe,
Zhao Li,
C.-J. Richard Shi,
Kartikeya Mayaram:
Symbolic Analysis of Nonlinear Analog Circuits.
DATE 2003: 11108-11109 |
| 42 | EE | Lei Yang,
C.-J. Richard Shi:
FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits.
ICCAD 2003: 741-747 |
| 41 | EE | Zhao Li,
C.-J. Richard Shi:
SILCA: Fast-Yet-Accurate Time-Domain Simulation of VLSI Circuits with Strong Parasitic Coupling Effects.
ICCAD 2003: 793-800 |
| 40 | EE | Sambuddha Bhattacharya,
C.-J. Richard Shi:
Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis.
ISCAS (4) 2003: 660-663 |
| 39 | EE | Nuttorn Jangkrajarng,
Sambuddha Bhattacharya,
Roy Hartono,
C.-J. Richard Shi:
Automatic analog layout retargeting for new processes and device sizes.
ISCAS (4) 2003: 704-707 |
| 38 | | Pavel V. Nikitin,
Winnie Yam,
C.-J. Richard Shi:
Parametric Equivalent Circuit Extraction for VLSI Structures.
VLSI-SOC 2003: 198-203 |
| 37 | EE | Sheldon X.-D. Tan,
C.-J. Richard Shi,
Jyh-Chwen Lee:
Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(12): 1678-1684 (2003) |
| 36 | EE | Sheldon X.-D. Tan,
C.-J. Richard Shi:
Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 277-284 (2003) |
| 35 | EE | Sheldon X.-D. Tan,
C.-J. Richard Shi:
Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis.
Integration 34(1-2): 65-86 (2003) |
| 34 | EE | Nuttorn Jangkrajarng,
Sambuddha Bhattacharya,
Roy Hartono,
C.-J. Richard Shi:
IPRAIL - intellectual property reuse-based analog IC layout automation.
Integration 36(4): 237-262 (2003) |
| 2002 |
|---|
| 33 | EE | Vikram Jandhyala,
Yong Wang,
Dipanjan Gope,
C.-J. Richard Shi:
Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular Meshes.
ISQED 2002: 38-42 |
| 2001 |
|---|
| 32 | EE | Sheldon X.-D. Tan,
C.-J. Richard Shi:
Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling.
DAC 2001: 550-554 |
| 31 | | Dragos Lungeanu,
C.-J. Richard Shi:
Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal Circuits.
ICCD 2001: 302-307 |
| 30 | | Alicia Manthe,
C.-J. Richard Shi:
Lower Bound Based DDD Minimization for Efficient Symbolic Circuit Analysis.
ICCD 2001: 374-379 |
| 29 | EE | C.-J. Richard Shi,
Sheldon X.-D. Tan:
Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 813-827 (2001) |
| 2000 |
|---|
| 28 | EE | Xiang-Dong Tan,
C.-J. Richard Shi:
Symbolic circuit-noise analysis and modeling with determinant decision diagrams.
ASP-DAC 2000: 283-288 |
| 27 | EE | Tao Pi,
C.-J. Richard Shi:
Analog-testability analysis by determinant-decision-diagrams based symbolic analysis.
ASP-DAC 2000: 541-546 |
| 26 | EE | Tao Pi,
C.-J. Richard Shi:
Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits.
DAC 2000: 19-22 |
| 25 | EE | Youcef Bourai,
C.-J. Richard Shi:
Layout Compaction for Yield Optimization via Critical Area Minimization.
DATE 2000: 122- |
| 24 | EE | Dragos Lungeanu,
C.-J. Richard Shi:
Parallel and Distributed VHDL Simulation.
DATE 2000: 658-662 |
| 23 | EE | C.-J. Richard Shi,
Sheldon X.-D. Tan:
Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 1-18 (2000) |
| 22 | EE | Sheldon X.-D. Tan,
C.-J. Richard Shi:
Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 401-412 (2000) |
| 1999 |
|---|
| 21 | EE | Xiang-Dong Tan,
C.-J. Richard Shi:
Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis.
ASP-DAC 1999: 1-4 |
| 20 | EE | Youcef Bourai,
C.-J. Richard Shi:
Symmetry Detection for Automatic Analog-Layout Recycling.
ASP-DAC 1999: 5-8 |
| 19 | EE | Xiang-Dong Tan,
C.-J. Richard Shi,
Dragos Lungeanu,
Jyh-Chwen Lee,
Li-Pen Yuan:
Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings.
DAC 1999: 78-83 |
| 18 | EE | Xiang-Dong Tan,
C.-J. Richard Shi:
Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams.
DATE 1999: 448-453 |
| 17 | EE | Dragos Lungeanu,
C.-J. Richard Shi:
Distributed simulation of VLSI systems via lookahead-free self-adaptive optimistic and conservative synchronization.
ICCAD 1999: 500-504 |
| 16 | EE | C.-J. Richard Shi,
Michael W. Tian:
Simulation and sensitivity of linear analog circuits under parameter variations by Robust interval analysis.
ACM Trans. Design Autom. Electr. Syst. 4(3): 280-312 (1999) |
| 15 | EE | C.-J. Richard Shi,
Janusz A. Brzozowski:
A Characterization of Signed Hypergraphs and Its Applications to VLSI Via Minimization and Logic Synthesis.
Discrete Applied Mathematics 90(1-3): 223-243 (1999) |
| 1998 |
|---|
| 14 | | C.-J. Richard Shi,
Michael W. Tian:
Automatic Test Generation for Linear Analog Circuits under Parameter Variations.
ASP-DAC 1998: 501-506 |
| 13 | | C.-J. Richard Shi:
Mixed-Signal Hardware Description Languages in the Era of System-on-Silicon: Challenges and Opportunities (Abstract of Embedded Tutorial).
ASP-DAC 1998: 543 |
| 12 | EE | Michael W. Tian,
C.-J. Richard Shi:
Efficient DC Fault Simulation of Nonlinear Analog Circuits.
DATE 1998: 899-904 |
| 11 | EE | Michael W. Tian,
C.-J. Richard Shi:
Nonlinear Analog DC Fault Simulation by One-Step Relaxation.
VTS 1998: 126-131 |
| 10 | EE | C.-J. Richard Shi,
Janusz A. Brzozowski:
Cluster-cover a theoretical framework for a class of VLSI-CAD optimization problems.
ACM Trans. Design Autom. Electr. Syst. 3(1): 76-107 (1998) |
| 9 | EE | Nihal J. Godambe,
C.-J. Richard Shi:
Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS.
J. Electronic Testing 13(1): 7-17 (1998) |
| 8 | EE | C.-J. Richard Shi:
Entity Overloading for Mixed-Signal Abstraction in VHDL.
J. Inf. Sci. Eng. 14(3): 633-644 (1998) |
| 1997 |
|---|
| 7 | EE | Michael W. Tian,
C.-J. Richard Shi:
Rapid Frequency-Domain Analog Fault Simulation Under Parameter Tolerances.
DAC 1997: 275-280 |
| 6 | EE | C.-J. Richard Shi,
Xiang-Dong Tan:
Symbolic analysis of large analog circuits with determinant decision diagrams.
ICCAD 1997: 366-373 |
| 5 | EE | Nihal J. Godambe,
C.-J. Richard Shi:
Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS.
VTS 1997: 177-183 |
| 4 | | C.-J. Richard Shi,
Anthony Vannelli,
Jiri Vlach:
Performance-Driven Layer Assignment by Integer Linear Programming and Path-Constrained Hypergraph Partitioning.
J. Heuristics 3(3): 225-243 (1997) |
| 1996 |
|---|
| 3 | EE | Olivier Coudert,
C.-J. Richard Shi:
Exact Dichotomy-based Constrained Encodi.
ICCD 1996: 426-431 |
| 1995 |
|---|
| 2 | EE | C.-J. Richard Shi,
Janusz A. Brzozowski:
A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems.
ASP-DAC 1995 |
| 1991 |
|---|
| 1 | EE | Jiri Vlach,
James A. Barby,
Anthony Vannelli,
T. Talkhan,
C.-J. Richard Shi:
Group delay as an estimate of delay in logic.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(7): 949-953 (1991) |
