| |
| 2006 | ||
|---|---|---|
| 2 | EE | Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, J. Piaget, N. Venkateswaran, Jeffrey G. Hemmett: First-Order Incremental Block-Based Statistical Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2170-2180 (2006) |
| 2004 | ||
| 1 | EE | Chandramouli Visweswariah, K. Ravindran, K. Kalafala, Steven G. Walker, S. Narayan: First-order incremental block-based statistical timing analysis. DAC 2004: 331-336 |
| 1 | Daniel K. Beece | [2] |
| 2 | Jeffrey G. Hemmett | [2] |
| 3 | K. Kalafala | [1] [2] |
| 4 | J. Piaget | [2] |
| 5 | K. Ravindran | [1] [2] |
| 6 | N. Venkateswaran | [2] |
| 7 | Chandramouli Visweswariah | [1] [2] |
| 8 | Steven G. Walker | [1] [2] |