| 2009 |
|---|
| 14 | EE | Haralampos-G. D. Stratigopoulos,
Salvador Mir,
Ahcène Bounceur:
Evaluation of Analog/RF Test Measurements at the Design Stage.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 582-590 (2009) |
| 2008 |
|---|
| 13 | EE | Haralampos-G. D. Stratigopoulos,
Jeanne Tongbong,
Salvador Mir:
A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation.
DATE 2008: 68-73 |
| 12 | EE | James Dardig,
Haralampos-G. D. Stratigopoulos,
Eric Stern,
Mark Reed,
Yiorgos Makris:
A Statistical Approach to Characterizing and Testing Functionalized Nanowires.
VTS 2008: 267-274 |
| 11 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 339-351 (2008) |
| 2007 |
|---|
| 10 | EE | Haralampos-G. D. Stratigopoulos,
Petros Drineas,
Mustapha Slamani,
Yiorgos Makris:
Non-RF to RF Test Correlation Using Learning Machines: A Case Study.
VTS 2007: 9-14 |
| 2006 |
|---|
| 9 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing.
VTS 2006: 406-411 |
| 8 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
Concurrent detection of erroneous responses in linear analog circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 878-891 (2006) |
| 2005 |
|---|
| 7 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
Generating decision regions in analog measurement spaces.
ACM Great Lakes Symposium on VLSI 2005: 88-91 |
| 6 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
Constructive Derivation of Analog Specification Test Criteria.
VTS 2005: 395-400 |
| 5 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
Nonlinear decision boundaries for testing analog circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1760-1773 (2005) |
| 2004 |
|---|
| 4 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
An Analog Checker with Input-Relative Tolerance for Duplicate Signals.
J. Electronic Testing 20(5): 479-488 (2004) |
| 2003 |
|---|
| 3 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
An Analog Checker With Input-Relative Tolerance for Duplicate Signals.
IOLTS 2003: 54- |
| 2 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
Concurrent Error Detection in Linear Analog Circuits Using State Estimation.
ITC 2003: 1164-1173 |
| 1 | EE | Haralampos-G. D. Stratigopoulos,
Yiorgos Makris:
An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits.
VTS 2003: 209-218 |
