2008 | ||
---|---|---|
67 | EE | Weibo Hu, Chung-Len Lee, Xin'an Wang: Arbitrary Waveform Generator Based on Direct Digital Frequency Synthesizer. DELTA 2008: 567-570 |
66 | EE | Jian Ruan, Chung-Len Lee: A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application. DELTA 2008: 99-102 |
65 | EE | Li-Rong Wang, Yi-Wei Chiu, Chia-Lin Hu, Ming-Hsien Tu, Shyh-Jye Jou, Chung-Len Lee: A reconfigurable MAC architecture implemented with mixed-Vt standard cell library. ISCAS 2008: 3426-3429 |
2007 | ||
64 | EE | Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen: Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1625-1636 (2007) |
63 | EE | Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen: IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. J. Electronic Testing 23(4): 341-355 (2007) |
2006 | ||
62 | EE | Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen: IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC 2006: 366-371 |
61 | EE | Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen: IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2513-2525 (2006) |
2005 | ||
60 | EE | Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen: Oscillation ring based interconnect test scheme for SOC. ASP-DAC 2005: 184-187 |
59 | EE | Ming Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu: Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle. Asian Test Symposium 2005: 106-111 |
58 | EE | Shih Ping Lin, Chung-Len Lee, Jwu E. Chen: A Scan Matrix Design for Low Power Scan-Based Test. Asian Test Symposium 2005: 224-229 |
57 | EE | Shih Ping Lin, Chung-Len Lee, Jwu E. Chen: Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing. Asian Test Symposium 2005: 324-329 |
56 | EE | Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen: Finite State Machine Synthesis for At-Speed Oscillation Testability. Asian Test Symposium 2005: 360-365 |
55 | EE | Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen: Multilevel full-chip routing with testability and yield enhancement. SLIP 2005: 29-36 |
54 | EE | Ming Shae Wu, Chung-Len Lee: Using a Periodic Square Wave Test Signal to Detect Crosstalk Faults. IEEE Design & Test of Computers 22(2): 160-169 (2005) |
2004 | ||
53 | EE | Chung Liang Chen, Chung-Len Lee, Ming Shae Wu: A New Path Delay Test Scheme Based on Path Delay Inertia. Asian Test Symposium 2004: 140-144 |
52 | EE | Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen: A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. Asian Test Symposium 2004: 145-150 |
51 | EE | Guan-Xun Chen, Chung-Len Lee, Jwu E. Chen: A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC. Asian Test Symposium 2004: 58-61 |
2003 | ||
50 | EE | Chin-Cheng Tsai, Chung-Len Lee: An On-Chip Jitter Measurement Circuit for the PLL. Asian Test Symposium 2003: 332-335 |
49 | EE | Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen: Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits. J. Inf. Sci. Eng. 19(4): 637-651 (2003) |
2002 | ||
48 | EE | Ming Shae Wu, Chung-Len Lee, Chi Peng Chang, Jwu E. Chen: A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal. Asian Test Symposium 2002: 170-175 |
47 | EE | Jun-Weir Lin, Chung-Len Lee, Jwu E. Chen: An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits. DATE 2002: 1119 |
46 | EE | Chih-Wen Lu, Chung-Len Lee: A Low Power High Speed Class-B Buffer Amplifier for Flat Panel Display Application. DELTA 2002: 172-176 |
45 | EE | Chih-Wen Lu, Chung-Len Lee: A low-power high-speed class-AB buffer amplifier for flat-panel-display application. IEEE Trans. VLSI Syst. 10(2): 163-168 (2002) |
44 | EE | Chih-Wen Lu, Chung-Len Lee, Chauchin Su, Jwu-E Chen: Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing. J. Electronic Testing 18(1): 89-97 (2002) |
43 | EE | Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen: Structural Fault Based Specification Reduction for Testing Analog Circuits. J. Electronic Testing 18(6): 571-581 (2002) |
2001 | ||
42 | EE | Chauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee: A computer aided engineering system for memory BIST. ASP-DAC 2001: 492-495 |
41 | EE | Tek Jau Tan, Chung-Len Lee: Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment. VTS 2001: 158-162 |
40 | EE | Jun-Weir Lin, Chung-Len Lee, Chau-chin Su, Jwu E. Chen: Fault Diagnosis for Linear Analog Circuits. J. Electronic Testing 17(6): 483-494 (2001) |
2000 | ||
39 | EE | Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen: Fault diagnosis for linear analog circuits. Asian Test Symposium 2000: 25-30 |
38 | EE | Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen: Is IDDQ testing not applicable for deep submicron VLSI in year 2011? Asian Test Symposium 2000: 338-343 |
37 | EE | Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su: A methodology for fault model development for hierarchical linear systems. Asian Test Symposium 2000: 90-95 |
36 | EE | Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee: All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses. DATE 2000: 527- |
35 | EE | Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir: Oscillation Ring Delay Test for High Performance Microprocessors. J. Electronic Testing 16(1-2): 147-155 (2000) |
34 | EE | Hsing-Chung Liang, Chung-Len Lee: Flip-Flop Selection for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits. J. Inf. Sci. Eng. 16(5): 687-702 (2000) |
33 | EE | Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su: A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. J. Inf. Sci. Eng. 16(5): 751-766 (2000) |
1999 | ||
32 | EE | Hsing-Chung Liang, Chung-Len Lee: An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits. Asian Test Symposium 1999: 173-178 |
31 | EE | Chauchin Su, Yue-Tsang Chen, Chung-Len Lee: Analog Metrology and Stimulus Selection in a Noisy Environment. Asian Test Symposium 1999: 233-238 |
30 | EE | Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen: A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model. J. Inf. Sci. Eng. 15(6): 885-897 (1999) |
1998 | ||
29 | EE | Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen: Maximization of power dissipation under random excitation for burn-in testing. ITC 1998: 567-576 |
28 | EE | Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen: Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. VTS 1998: 341-347 |
27 | EE | Wen Ching Wu, Chung-Len Lee, Jwu E. Chen: A Two-Phase Fault Simulation Scheme for Sequential Circuits. J. Inf. Sci. Eng. 14(3): 669-686 (1998) |
1997 | ||
26 | EE | Chih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen: Fault diagnosis of odd-even sorting networks. Asian Test Symposium 1997: 288- |
25 | EE | Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen: Functional test pattern generation for CMOS operational amplifier. VTS 1997: 267-273 |
24 | EE | Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen: Identifying invalid states for sequential circuit test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 1025-1033 (1997) |
1996 | ||
23 | EE | Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen: Invalid State Identification for Sequential Circuit Test Generation. Asian Test Symposium 1996: 10-15 |
22 | Chung-Len Lee, Meng-Lieh Sheu: A Multiple-Sequence Generator Based on Inverted Nonlinear Autonomous Machines. IEEE Trans. Computers 45(9): 1079-1083 (1996) | |
1995 | ||
21 | EE | Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, P. Pal Chaudhuri: Panel: New Research Problems in the Emerging Test Technology. Asian Test Symposium 1995: 189- |
20 | EE | Wen Ching Wu, Chung-Len Lee, Jwu E. Chen: Identification of robust untestable path delay faults. Asian Test Symposium 1995: 229- |
19 | EE | Meng-Lieh Sheu, Chung-Len Lee: A programmable multiple-sequence generator for BIST applications. Asian Test Symposium 1995: 279-285 |
18 | EE | Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen: Fanout fault analysis for digital logic circuits. Asian Test Symposium 1995: 33-39 |
17 | EE | Hui Min Wang, Chung-Len Lee, Jwu E. Chen: Factorization of Multi-Valued Logic Functions. ISMVL 1995: 164-169 |
16 | EE | Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang: On Designing of 4-Valued Memory with Double-Gate TFT. ISMVL 1995: 187- |
15 | EE | Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen: Identifying Untestable Faults in Sequential Circuits. IEEE Design & Test of Computers 12(3): 14-23 (1995) |
14 | EE | Beyin Chen, Chung-Len Lee: Universal test set generation for CMOS circuits. J. Electronic Testing 6(3): 313-323 (1995) |
1994 | ||
13 | Meng Chiy Lin, Jwu E. Chen, Chung-Len Lee: TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator. EDAC-ETC-EUROASIC 1994: 508-512 | |
12 | Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin: Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. EDAC-ETC-EUROASIC 1994: 661 | |
11 | Hui Min Wang, Chung-Len Lee, Jwu E. Chen: Complete Test Set for Multiple-Valued Logic Networks. ISMVL 1994: 289-296 | |
10 | Yeong-Jar Chang, Chung-Len Lee: Synthesis of Multi-Variable MVL Funtions Using Hybrid Mode CMOS Logic. ISMVL 1994: 35-41 | |
9 | Hui Min Wang, Chung-Len Lee, Jwu E. Chen: Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits. ISMVL 1994: 44-51 | |
8 | Meng-Lieh Sheu, Chung-Len Lee: Simplifying Sequential Circuit Test Generation. IEEE Design & Test of Computers 11(3): 28-38 (1994) | |
7 | EE | Beyin Chen, Chung-Len Lee: A complement-based fast algorithm to generate universal test sets for multi-output functions. IEEE Trans. on CAD of Integrated Circuits and Systems 13(3): 370-377 (1994) |
1992 | ||
6 | Hui Min Wang, Chung-Len Lee, Jwu E. Chen: Fault Analysis on Two-Level (K+1)-Valued Logic Circuits. ISMVL 1992: 181-188 | |
5 | EE | Chung-Len Lee, Ching Ping Wu, Wen-Zen Shen, Tyh-Song Hwang, Shueng Dar Hwang: MT-SIM a mixed-level transition fault simulator based on parallel patterns. J. Electronic Testing 3(1): 67-78 (1992) |
1991 | ||
4 | EE | Wen Ching Wu, Chung-Len Lee: A Probabilistic Testability Measure for Delay Faults. DAC 1991: 440-445 |
3 | EE | Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen: Single-fault fault-collapsing analysis in sequential logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(12): 1559-1568 (1991) |
2 | EE | Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen: Checkpoints in irredundant two-level combinational circuits. J. Electronic Testing 2(4): 395-397 (1991) |
1990 | ||
1 | EE | Tyh-Song Hwang, Chung-Len Lee, Wen-Zen Shen, Ching Ping Wu: A Parallel Pattern Mixed-Level Fault Simulator. DAC 1990: 716-719 |