2008 |
20 | EE | Ravishankar Rao,
Sarma B. K. Vrudhula:
Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors.
ICCAD 2008: 537-542 |
19 | EE | Ravishankar Rao,
Sarma B. K. Vrudhula,
Krzysztof S. Berezowski:
Analytical results for design space exploration of multi-core processors employing thread migration.
ISLPED 2008: 229-232 |
2007 |
18 | EE | Ravishankar Rao,
Sarma B. K. Vrudhula:
Performance optimal processor throttling under thermal constraints.
CASES 2007: 257-266 |
17 | EE | Ravishankar Rao,
Sarma B. K. Vrudhula,
Chaitali Chakrabarti:
Throughput of multi-core processors under thermal constraints.
ISLPED 2007: 201-206 |
16 | EE | Ravishankar Rao,
Sarma B. K. Vrudhula:
Energy optimal speed control of a producer--consumer device pair.
ACM Trans. Embedded Comput. Syst. 6(4): (2007) |
2006 |
15 | EE | John Oliver,
Ravishankar Rao,
Michael Brown,
Jennifer Mankin,
Diana Franklin,
Frederic T. Chong,
Venkatesh Akella:
Tile size selection for low-power tile-based architectures.
Conf. Computing Frontiers 2006: 83-94 |
14 | EE | Ravishankar Rao,
Justin Wenck,
Diana Franklin,
Rajeevan Amirtharajah,
Venkatesh Akella:
Segmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns.
HiPC 2006: 123-134 |
13 | EE | Ravishankar Rao,
Sarma B. K. Vrudhula,
Chaitali Chakrabarti,
Naehyuck Chang:
An optimal analytical solution for processor speed control with thermal constraints.
ISLPED 2006: 292-297 |
12 | EE | Ravishankar Rao,
Sarma B. K. Vrudhula:
Energy-Optimal Speed Control of a Generic Device.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2737-2746 (2006) |
11 | EE | John Oliver,
Ravishankar Rao,
Diana Franklin,
Frederic T. Chong,
Venkatesh Akella:
Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications.
J. Embedded Computing 2(2): 157-166 (2006) |
2005 |
10 | EE | Vineet Agarwal,
Navneeth Kankani,
Ravishankar Rao,
Sarvesh Bhardwaj,
Janet Meiling Wang:
An efficient combinationality check technique for the synthesis of cyclic combinational circuits.
ASP-DAC 2005: 212-215 |
9 | EE | Ravishankar Rao,
Sarma B. K. Vrudhula:
Energy optimal speed control of devices with discrete speed sets.
DAC 2005: 901-904 |
8 | | Ravishankar Rao,
Sarma B. K. Vrudhula:
Battery optimization vs energy optimization: which to choose and when?
ICCAD 2005: 439-445 |
2004 |
7 | EE | Ravishankar Rao,
Sarma B. K. Vrudhula,
Musaravakkam S. Krishnan:
Disk drive energy optimization for audio-video applications.
CASES 2004: 93-103 |
6 | EE | Ravishankar Rao,
Sarma B. K. Vrudhula:
Energy optimization for a two-device data flow chain.
ICCAD 2004: 268-274 |
5 | EE | John Oliver,
Ravishankar Rao,
Paul Sultana,
Jedidiah R. Crandall,
Erik Czernikowski,
Leslie W. Jones IV,
Diana Franklin,
Venkatesh Akella,
Frederic T. Chong:
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor.
ISCA 2004: 150-161 |
2003 |
4 | EE | Ravishankar Rao,
Sarma B. K. Vrudhula,
Daler N. Rakhmatov:
Analysis of discharge techniques for multiple battery systems.
ISLPED 2003: 44-47 |
3 | EE | John Oliver,
Ravishankar Rao,
Paul Sultana,
Jedidiah R. Crandall,
Erik Czernikowski,
Leslie W. Jones IV,
Dean Copsey,
Diana Keen,
Venkatesh Akella,
Frederic T. Chong:
Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture.
PACS 2003: 73-85 |
2 | EE | Ravishankar Rao,
Sarma B. K. Vrudhula,
Daler N. Rakhmatov:
Battery Modeling for Energy-Aware System Design.
IEEE Computer 36(12): 77-87 (2003) |
2002 |
1 | EE | Ravishankar Rao,
Mark Oskin,
Frederic T. Chong:
HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space.
HiPC 2002: 620-629 |