IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 26

Volume 26, Number 1, January 2007

• Enrico Macii:
  Editorial. 1
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• Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi:
  Robust Analog/RF Circuit Design With Projection-Based Performance Modeling. 2-15
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• Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi:
  Asymptotic Probability Extraction for Nonnormal Performance Distributions. 16-37
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• Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh:
  Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs. 38-52
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• Akhilesh Kumar, Mohab Anis:
  Dual-Threshold CAD Framework for Subthreshold Leakage Power Aware FPGAs. 53-66
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• Ashish Srivastava, T. Kachru, Dennis Sylvester:
  Low-Power-Design Space Exploration Considering Process Variation Using Robust Optimization. 67-79
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• Shinji Odanaka:
  A High-Resolution Method for Quantum Confinement Transport Simulations in MOSFETs. 80-85
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• Yonghong Yang, Zhenyu (Peter) Gu, Changyun Zhu, Robert P. Dick, Li Shang:
  ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis. 86-99
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• Zai-Fa Zhou, Qing-An Huang, Wei-Hua Li, Wei Lu:
  A Novel 3-D Dynamic Cellular Automata Model for Photoresist-Etching Process Simulation. 100-114
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• Charles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky:
  Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction. 115-126
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• Devang Jariwala, John Lillis:
  RBI: Simultaneous Placement and Routing Optimization Technique. 127-141
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• Taewhan Kim, Jungeun Kim:
  Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization. 142-151
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• Kai-Hui Chang, Valeria Bertacco, Igor L. Markov:
  Simulation-Based Bug Trace Minimization With BMC-Based Refinement. 152-165
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• Wendemagegnehu T. Beyene:
  Application of Artificial Neural Networks to Statistical Analysis and Nonlinear Modeling of High-Speed Interconnect Systems. 166-176
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• Kyosun Kim, Kaijie Wu, Ramesh Karri:
  The Robust QCA Adder Designs Using Composable QCA Building Blocks. 176-183
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• Dipanjan Sengupta, Resve Saleh:
  Generalized Power-Delay Metrics in Deep Submicron CMOS Designs. 183-189
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• B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal:
  A New ATPG Technique (ExpoTan) for Testing Analog Circuits. 189-196
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Volume 26, Number 2, February 2007

• Kia Bazargan, André DeHon:
  Guest Editorial. 201-202
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• Ian Kuon, Jonathan Rose:
  Measuring the Gap Between FPGAs and ASICs. 203-215
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• Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, Simon Wong:
  Performance Benefits of Monolithically Stacked 3-D FPGA. 216-229
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• Jason Cong, Kirill Minkovich:
  Optimality Study of Logic Synthesis for LUT-Based FPGAs. 230-239
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• Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton:
  Improvements to Technology Mapping for LUT-Based FPGAs. 240-253
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• Welson Sun, Michael J. Wirthlin, Stephen Neuendorffer:
  FPGA Pipeline Synthesis Design Exploration Using Module Selection and Resource Sharing. 254-265
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• Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose:
  Exploration and Customization of FPGA-Based Soft Processors. 266-277
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• Russell Tessier, Vaughn Betz, David Neto, Aaron Egier, Thiagaraja Gopalsamy:
  Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks. 278-290
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• Mark Holland, Scott Hauck:
  Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC. 291-295
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• Tim Tuan, A. Rahman, Satyaki Das, Steven Trimberger, Sean Kao:
  A 90-nm Low-Power FPGA for Battery-Powered Applications. 296-300
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• Andrew B. Kahng, Ion I. Mandoiu, Xu Xu, Alexander Zelikovsky:
  Enhanced Design Flow and Optimizations for Multiproject Wafers. 301-311
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• Ismail Kadayif, Partho Nath, Mahmut T. Kandemir, Anand Sivasubramaniam:
  Reducing Data TLB Power via Compiler-Directed Address Generation. 312-324
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• Baohua Wang, Pinaki Mazumder:
  Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function. 325-344
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• Yih-Lang Li, Jin-Yih Li, Wen-Bin Chen:
  An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow. 345-358
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• Xiaoyong Chen, Douglas L. Maskell, Yang Sun:
  Fast Identification of Custom Instructions for Extensible Processors. 359-368
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• Dongkun Shin, Jihong Kim:
  Optimizing Intratask Voltage Scheduling Using Profile and Data-Flow Information. 369-385
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• Kedarnath J. Balakrishnan, Nur A. Touba:
  Relationship Between Entropy and Test Data Compression. 386-395
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• Jinkyu Lee, Nur A. Touba:
  LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test. 396-401
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Volume 26, Number 3, March 2007

• Georges G. E. Gielen, Donatella Sciuto:
  Guest Editorial [intro. to the special issue on the 2006 IEEE/ACM Design, Automation and Test in Europe Conference]. 405-407
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• Sudeep Pasricha, Nikil D. Dutt:
  A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC. 408-420
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• Federico Angiolini, Paolo Meloni, Salvatore Carta, Luigi Raffo, Luca Benini:
  A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs. 421-434
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• Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne:
  Introduction of Architecturally Visible Storage in Instruction Set Extensions. 435-446
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• Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou:
  Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. 447-455
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• Cristian Soviani, Olivier Tardieu, Stephen A. Edwards:
  Optimizing Sequential Cycles Through Shannon Decomposition and Retiming. 456-467
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• Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester:
  Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. 468-479
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• Ying Wei, Alex Doboli, Hua Tang:
  Systematic Methodology for Designing Reconfigurable DeltaSigma Modulator Topologies for Multimode Communication Systems. 480-496
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• Enrico Giunchiglia, Massimo Narizzano, Armando Tacchella:
  Quantifier Structure in Search-Based Procedures for QBFs. 497-507
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• Li Shang, Robert P. Dick, Niraj K. Jha:
  SLOPES: Hardware-Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs. 508-526
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• Chao-Yang Yeh, Malgorzata Marek-Sadowska:
  Timing-Aware Power-Noise Reduction in Placement. 527-541
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• Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
  Automated Energy/Performance Macromodeling of Embedded Software. 542-552
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• Mehdi Baradaran Tahoori, Subhasish Mitra:
  Application-Dependent Delay Testing of FPGAs. 553-563
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• Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu:
  Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment. 564-573
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• Farid N. Najm, Noel Menezes, Imad A. Ferzli:
  A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis. 574-591
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• Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda:
  Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. 592-605
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• B. P. Harish, Navakanta Bhat, Mahesh B. Patil:
  On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology. 606-614
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Volume 26, Number 4, April 2007

• J. Hu, Patrick H. Madden:
  Guest Editorial. 617-618
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• Jinjun Xiong, Vladimir Zolotov, Lei He:
  Robust Extraction of Spatial Correlation. 619-631
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• Jarrod A. Roy, Igor L. Markov:
  Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement. 632-644
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• Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
  Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. 645-658
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• Shinichi Koda, Chikaaki Kodama, Kunihiro Fujiyoshi:
  Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout. 659-668
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• Jianhua Li, Laleh Behjat, Andrew A. Kennings:
  Net Cluster: A Net-Reduction-Based Clustering Preprocessing Algorithm for Partitioning and Placement. 669-679
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• Jin Shi, Yici Cai, Sheldon X.-D. Tan, Jeffrey Fan, Xianlong Hong:
  Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis. 680-692
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• Chen-Wei Liu, Yao-Wen Chang:
  Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence. 693-704
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• Yih-Lang Li, Hsin-Yu Chen, Chih-Ta Lin:
  NEMO: A New Implicit-Connection-Graph-Based Gridless Router With Multilayer Planes and Pseudo Tile Propagation. 705-718
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• Bor-Yiing Su, Yao-Wen Chang, Jiang Hu:
  An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles. 719-733
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• Jun Chen, Lei He:
  Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity. 734-738
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• Jinjun Xiong, Lei He:
  Probabilistic Transitive-Closure Ordering and Its Application on Variational Buffer Insertion. 739-742
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• Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy:
  Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits. 743-751
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• Fei Li, Yan Lin, Lei He:
  Field Programmability of Supply Voltages for FPGA Power Reduction. 752-764
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• Hiren D. Patel, Sandeep K. Shukla, Reinaldo A. Bergamaschi:
  Heterogeneous Behavioral Hierarchy Extensions for SystemC. 765-780
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• Benny Thörnberg, Martin Palkovic, Qubo Hu, Leif Olsson, Per Gunnar Kjeldsberg, Mattias O'Nils, Francky Catthoor:
  Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems. 781-800
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• B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine:
  Temperature- and Voltage-Aware Timing Analysis. 801-815
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Volume 26, Number 5, May 2007

• Chen He, Margarida F. Jacome:
  Defect-Aware High-Level Synthesis Targeted at Reconfigurable Nanofabrics. 817-833
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• Martin Saint-Laurent:
  A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures. 834-844
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• Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong:
  Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random L_eff Variation. 845-857
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• Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden:
  Routability-Driven Placement and White Space Allocation. 858-871
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• Zhuo Li, Ying Zhou, Weiping Shi:
  Wire Sizing for Non-Tree Topology. 872-880
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• Zhengyong Zhu, He Peng, Chung-Kuan Cheng, Khosro Rouz, Manjit Borah, Ernest S. Kuh:
  Two-Stage Newton-Raphson Method for Transistor-Level Simulation. 881-895
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• Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler:
  Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers. 896-906
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• Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Erik Chmelar, M. Grinchuk, Arun Gunda:
  Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration. 907-918
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• Jin-Fu Li:
  Testing Ternary Content Addressable Memories With Comparison Faults Using March-Like Tests. 919-931
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• Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng:
  Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern Generation. 932-942
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• Mohammad Tehranipoor, Reza M. Rad:
  Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based Nanofabrics. 943-958
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• Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng:
  Efficient Timing Analysis With Known False Paths Using Biclique Covering. 959-969
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• Saihua Lin, Huazhong Yang, Rong Luo:
  A Novel gamma d/n, RLCG Transmission Line Model Considering Complex RC(L) Loads. 970-977
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• Srinivasa R. Sridhara, Naresh R. Shanbhag:
  Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes. 977-982
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• Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas:
  High-Quality Transition Fault ATPG for Small Delay Defects. 983-989
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Volume 26, Number 6, May 2007

• Danil Sokolov, Alexandre V. Bystrov, Alexandre Yakovlev:
  Direct Mapping of Low-Latency Asynchronous Controllers From STGs. 993-1009
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• Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner:
  Ant Colony Optimizations for Resource- and Timing-Constrained Operation Scheduling. 1010-1029
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• Youngjin Cho, Naehyuck Chang:
  Energy-Aware Clock-Frequency Assignment in Microprocessors and Memory Devices for Dynamic Voltage Scaling. 1030-1040
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• Tai-Chen Chen, Yao-Wen Chang:
  Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction. 1041-1053
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• Ting Mei, Jaijeet S. Roychowdhury:
  Small-Signal Analysis of Oscillators Using Generalized Multitime Partial Differential Equations. 1054-1069
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• Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
  Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores. 1070-1083
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• Wei Pei, Wen-Ben Jone, Yiming Hu:
  Fault Modeling and Detection for Drowsy SRAM Caches. 1084-1100
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• Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou, Cheng-Wen Wu:
  Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms. 1101-1113
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• Emre Salman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar, Eby G. Friedman:
  Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis. 1114-1125
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• Ilya Wagner, Valeria Bertacco, Todd M. Austin:
  Microprocessor Verification via Feedback-Adjusted Markov Models. 1126-1138
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• Changzhong Chen, Emad Gad, Natalie Nakhla, Ramachandra Achar:
  Analysis of Frequency-Dependent Interconnects Using Integrated Congruence Transform. 1139-1149
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• Ming-e Jing, Yue Hao, Dian Zhou, Xuan Zeng:
  A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm. 1149-1155
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• Yi-Yu Liu, TingTing Hwang:
  Crosstalk-Aware Domino-Logic Synthesis. 1155-1161
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• Jiong Luo, Niraj K. Jha:
  Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems. 1161-1170
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• Irith Pomeranz:
  Invariant States and Redundant Logic in Synchronous Sequential Circuits. 1171-1175
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Volume 26, Number 7, July 2007

• Tomohiro Yoneda, Chris J. Myers:
  Synthesis of Timed Circuits Based on Decomposition. 1177-1195
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• Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
  FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability. 1196-1210
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• Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong, Lei He:
  Device and Architecture Cooptimization for FPGA Power Reduction. 1211-1221
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• Chuan Lin, Hai Zhou:
  Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk. 1222-1232
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• Rui Zhang, Pallav Gupta, Niraj K. Jha:
  Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies. 1233-1245
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• Vishal Khandelwal, Ankur Srivastava:
  Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors. 1246-1255
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• Huaizhi Wu, Martin D. F. Wong, I-Min Liu, Yusu Wang:
  Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement. 1256-1269
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• Lili Zhou, Cherry Wakayama, C.-J. Richard Shi:
  CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits. 1270-1282
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• Srinivasan Murali, Luca Benini, Giovanni De Micheli:
  An Application-Specific Design Methodology for On-Chip Crossbar Generation. 1283-1296
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• Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli:
  Timing-Error-Tolerant Network-on-Chip Design Methodology. 1297-1310
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• Irith Pomeranz, Sudhakar M. Reddy:
  Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults. 1311-1319
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• Namrata Shekhar, Sudhakar Kalla, Florian Enescu:
  Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing. 1320-1330
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• Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya:
  An Efficient Scan Tree Design for Compact Test Pattern Set. 1331-1339
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• Loganathan Lingappan, Niraj K. Jha:
  Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. 1339-1345
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• Chin-Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
  Path-Based Buffer Insertion. 1346-1355
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Volume 26, Number 8, August 2007

• Alberto L. Sangiovanni-Vincentelli:
  Remembering Richard [Obituary, Richard A.Newton]. 1357-1366
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• Yongseok Choi, Naehyuck Chang, Taewhan Kim:
  DC-DC Converter-Aware Power Management for Low-Power Embedded Systems. 1367-1381
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• Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu, Lei He:
  TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits. 1382-1392
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• Bernard N. Sheehan:
  Realizable Reduction of RC Networks. 1393-1407
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• Michael Spevak, Tibor Grasser:
  Discretization of Macroscopic Transport Equations on Non-Cartesian Coordinate Systems. 1408-1416
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• Jia-Wei Fang, I-Jye Lin, Yao-Wen Chang, Jyh-Herng Wang:
  A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design. 1417-1429
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• Hsun-Cheng Lee, Yao-Wen Chang, Hannah Honghua Yang:
  MB^ast-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design. 1430-1444
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• Jia Wang, Hai Zhou:
  Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing. 1445-1453
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• Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane:
  BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC. 1454-1464
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• Fang Liu, Sule Ozev:
  Statistical Test Development for Analog Circuits Under High Process Variations. 1465-1477
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• Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
  Fault Diagnosis With Convolutional Compactors. 1478-1494
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• Soroush Abbaspour, Hanif Fatemi, Massoud Pedram:
  Parameterized Non-Gaussian Variational Gate Timing Analysis. 1495-1508
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• Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou:
  Observability Analysis on HDL Descriptions for Effective Functional Validation. 1509-1521
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• Debjit Sinha, Hai Zhou, Narendra V. Shenoy:
  Advances in Computation of the Maximum of a Set of Gaussian Random Variables. 1522-1533
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• Bernabé Linares-Barranco, Teresa Serrano-Gotarredona:
  On an Efficient CAD Implementation of the Distance Term in Pelgrom's Mismatch Model. 1534-1538
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• Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty:
  Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains. 1539-1547
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Volume 26, Number 9, August 2007

• Gustavo de Veciana, Marcello Lajolo, Chen He, Enrico Macii, Sachin S. Sapatnekar:
  In Memoriam: Margarida F. Jacome. 1549-1550
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• Peter Tummeltshammer, James C. Hoe, Markus Püschel:
  Time-Multiplexed Multiple-Constant Multiplication. 1551-1563
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• Chang Woo Kang, Ali Iranli, Massoud Pedram:
  A Synthesis Approach for Coarse-Grained Antifuse-Based FPGAs. 1564-1575
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• Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou:
  Unified Incremental Physical-Level and High-Level Synthesis. 1576-1588
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• Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias:
  Exploiting Bit-Level Delay Calculations to Soften Read-After-Write Dependences in Behavioral Synthesis. 1589-1601
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• James D. Ma, Rob A. Rutenbar:
  Interval-Valued Reduced-Order Statistical Interconnect Modeling. 1602-1613
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• Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester:
  Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation. 1614-1624
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• Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
  Multilevel Full-Chip Routing With Testability and Yield Enhancement. 1625-1636
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• Sanghamitra Roy, Weijen Chen, Charlie Chung-Ping Chen, Yu Hen Hu:
  Numerically Convex Forms and Their Application in Gate Sizing. 1637-1647
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• Dennis K. Y. Tong, Evangeline F. Y. Young, Chris C. N. Chu, Sampath Dechu:
  Wire Retiming Problem With Net Topology Optimization. 1648-1660
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• Yong Zhan, Sachin S. Sapatnekar:
  High-Efficiency Green Function-Based Thermal Simulation Algorithms. 1661-1675
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• Andreas Gerstlauer, Dongwan Shin, Junyu Peng, Rainer Dömer, Daniel Gajski:
  Automatic Layer-Based Generation of System-On-Chip Bus Communication Models. 1676-1687
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• Gunar Schirner, Rainer Dömer:
  Result-Oriented Modeling - A Novel Technique for Fast and Accurate TLM. 1688-1699
  Electronic Edition (link) BibTeX
• Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman:
  z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs. 1700-1712
  Electronic Edition (link) BibTeX
• Sultan M. Al-Harbi, Fadel Noor, Fadi M. Al-Turjman:
  March DSS: A New Diagnostic March Test for All Memory Simple Static Faults. 1713-1720
  Electronic Edition (link) BibTeX
• Sung Jin Cho, Un-Sook Choi, Han-Doo Kim, Yoon-Hee Hwang, Jin-Gyoung Kim, Seong-Hun Heo:
  New Synthesis of One-Dimensional 90/150 Linear Hybrid Group Cellular Automata. 1720-1724
  Electronic Edition (link) BibTeX
• Ngai Wong, Venkataramanan Balakrishnan:
  Fast Positive-Real Balanced Truncation Via Quadratic Alternating Direction Implicit Iteration. 1725-1731
  Electronic Edition (link) BibTeX

Volume 26, Number 10, October 2007

• Guido Stehr, Helmut E. Graeb, Kurt Antreich:
  Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination. 1733-1748
  Electronic Edition (link) BibTeX
• Felice Balarin, Roberto Passerone:
  Specification, Synthesis, and Simulation of Transactor Processes. 1749-1762
  Electronic Edition (link) BibTeX
• Bo Yang, Ramesh Karri:
  Power Optimization for Universal Hash Function Data Path Using Divide-and-Concatenate Technique. 1763-1769
  Electronic Edition (link) BibTeX
• Kunhyuk Kang, Haldun Kufluoglu, Kaushik Roy, Muhammad Ashraful Alam:
  Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis. 1770-1781
  Electronic Edition (link) BibTeX
• Sungjae Lee, Kevin J. Webb:
  A Correlated Diffusion Noise Model for the Field-Effect Transistor. 1782-1789
  Electronic Edition (link) BibTeX
• Murari Mani, Anirudh Devgan, Michael Orshansky, Yaping Zhan:
  A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits. 1790-1802
  Electronic Edition (link) BibTeX
• Love Singhal, Elaheh Bozorgzadeh, David Eppstein:
  Interconnect Criticality-Driven Delay Relaxation. 1803-1817
  Electronic Edition (link) BibTeX
• Bor-Yiing Su, Yao-Wen Chang:
  An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing. 1818-1829
  Electronic Edition (link) BibTeX
• Giovanni Beltrame, Donatella Sciuto, Cristina Silvano:
  Multi-Accuracy Power and Performance Transaction-Level Modeling. 1830-1842
  Electronic Edition (link) BibTeX
• Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
  Hybrid Simulation for Energy Estimation of Embedded Software. 1843-1854
  Electronic Edition (link) BibTeX
• R. Rashidzadeh, Majid Ahmadi, William C. Miller:
  Test and Measurement of Analog and RF Cores in Mixed-Signal SoC Environment. 1855-1865
  Electronic Edition (link) BibTeX
• Yu Cao, Lawrence T. Clark:
  Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach. 1866-1873
  Electronic Edition (link) BibTeX
• Andrew B. Kahng, Bao Liu, Xu Xu:
  Statistical Timing Analysis in the Presence of Signal-Integrity Effects. 1873-1877
  Electronic Edition (link) BibTeX
• Jayawant Kakade, Dimitrios Kagaris:
  Minimization of Linear Dependencies Through the Use of Phase Shifters. 1877-1882
  Electronic Edition (link) BibTeX
• Ja Chun Ku, Yehea I. Ismail:
  On the Scaling of Temperature-Dependent Effects. 1882-1888
  Electronic Edition (link) BibTeX
• Jin-Fu Li:
  Transparent-Test Methodologies for Random Access Memories Without/With ECC. 1888-1893
  Electronic Edition (link) BibTeX
• Debdeep Mukhopadhyay, Gaurav Sengar, Dipanwita Roy Chowdhury:
  Hierarchical Verification of Galois Field Circuits. 1893-1898
  Electronic Edition (link) BibTeX
• Fei Xu, Chip-Hong Chang, Ching-Chuen Jong:
  Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common Subexpressions. 1898-1907
  Electronic Edition (link) BibTeX

Volume 26, Number 11, November 2007

• Markus Wedler, Dominik Stoffel, Raik Brinkmann, Wolfgang Kunz:
  A Normalization Method for Arithmetic Data-Path Verification. 1909-1922
  Electronic Edition (link) BibTeX
• Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz:
  Improved Interval-Based Characterization of Fixed-Point LTI Systems With Feedback Loops. 1923-1933
  Electronic Edition (link) BibTeX
• Kazuo Aoyama:
  Design Methods for Symmetric Function Generators Based on Threshold Elements. 1934-1946
  Electronic Edition (link) BibTeX
• Swaroop Ghosh, Swarup Bhunia, Kaushik Roy:
  CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation. 1947-1956
  Electronic Edition (link) BibTeX
• Animesh Datta, Ashish Goel, R. T. Cakici, Hamid Mahmoodi, D. Lekshmanan, Kaushik Roy:
  Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices. 1957-1966
  Electronic Edition (link) BibTeX
• Luca De Marchi, Emanuele Baravelli, Francesco Franzè, Nicolo Speciale:
  Wavelet Adaptivity for 3-D Device Simulation. 1967-1977
  Electronic Edition (link) BibTeX
• Amitabh Chaudhary, Danny Z. Chen, Xiaobo Sharon Hu, Michael T. Niemier, Ramprasad Ravichandran, Kevin Whitton:
  Fabricatable Interconnect and Molecular QCA Circuits. 1978-1991
  Electronic Edition (link) BibTeX
• Sandip Aine, P. P. Chakrabarti, Rajeev Kumar:
  An Automated Meta-Level Control Framework for Optimizing the Quality-Time Tradeoff of VLSI Algorithms. 1992-2008
  Electronic Edition (link) BibTeX
• Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin-Ngai Sze:
  Fast Algorithms for Slew-Constrained Minimum Cost Buffering. 2009-2022
  Electronic Edition (link) BibTeX
• Eric Wong, Jacob R. Minz, Sung Kyu Lim:
  Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction. 2023-2034
  Electronic Edition (link) BibTeX
• Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
  A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors. 2035-2045
  Electronic Edition (link) BibTeX
• Salvador Manich, L. Garcia-Deiros, Joan Figueras:
  Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources. 2046-2058
  Electronic Edition (link) BibTeX
• Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy:
  Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits. 2059-2068
  Electronic Edition (link) BibTeX
• Ruiming Chen, Hai Zhou:
  An Effective Algorithm for Buffer Insertion in General Circuits Based on Network Flow. 2069-2073
  Electronic Edition (link) BibTeX
• Tom Tong Jing, Zhe Feng, Yu Hu, Xian-Long Hong, Xiaodong Hu, Guiying Yan:
  lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) Complexity. 2073-2079
  Electronic Edition (link) BibTeX
• Gaurav Sengar, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury:
  Secured Flipped Scan-Chain Model for Crypto-Architecture. 2080-2084
  Electronic Edition (link) BibTeX
• Kai Yang, Kwang-Ting Cheng:
  Silicon Debug for Timing Errors. 2084-2088
  Electronic Edition (link) BibTeX

Volume 26, Number 12, December 2007

• Wei Dong, Peng Li:
  Hierarchical Harmonic-Balance Methods for Frequency-Domain Analog-Circuit Analysis. 2089-2101
  Electronic Edition (link) BibTeX
• Aviral Shrivastava, Sanghyun Park, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek:
  Automatic Design Space Exploration of Register Bypasses in Embedded Processors. 2102-2115
  Electronic Edition (link) BibTeX
• Bradley N. Bond, Luca Daniel:
  A Piecewise-Linear Moment-Matching Approach to Parameterized Model-Order Reduction for Highly Nonlinear Systems. 2116-2129
  Electronic Edition (link) BibTeX
• Minsik Cho, David Z. Pan:
  BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP. 2130-2143
  Electronic Edition (link) BibTeX
• Puneet Gupta, Andrew B. Kahng, Chul-Hong Park:
  Detailed Placement for Enhanced Control of Resist and Etch CDs. 2144-2157
  Electronic Edition (link) BibTeX
• Haoxing Ren, David Z. Pan, Charles J. Alpert, Paul G. Villarrubia, Gi-Joon Nam:
  Diffusion-Based Placement Migration With Application on Legalization. 2158-2172
  Electronic Edition (link) BibTeX
• Jarrod A. Roy, Igor L. Markov:
  ECO-System: Embracing the Change in Placement. 2173-2185
  Electronic Edition (link) BibTeX
• Youngmin Yi, Dohyung Kim, Soonhoi Ha:
  Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual Synchronization. 2186-2200
  Electronic Edition (link) BibTeX
• Cristian Grecu, André Ivanov, Resve A. Saleh, Partha Pratim Pande:
  Testing Network-on-Chip Communication Fabrics. 2201-2214
  Electronic Edition (link) BibTeX
• Sanghyeon Baeg:
  Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks. 2215-2221
  Electronic Edition (link) BibTeX
• Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang, TingTing Hwang:
  A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design. 2222-2227
  Electronic Edition (link) BibTeX