| 2008 |
|---|
| 70 | EE | Francesc Moll,
Joan Figueras,
Antonio Rubio:
Data Dependence of Delay Distribution for a Planar Bus.
PATMOS 2008: 409-418 |
| 69 | EE | Daniel Arumí,
Rosa Rodríguez-Montañés,
Joan Figueras,
Stefan Eichenberger,
Camelia Hora,
Bram Kruseman:
Full Open Defects in Nanometric CMOS.
VTS 2008: 119-124 |
| 68 | EE | Daniel Arumí,
Rosa Rodríguez-Montañés,
Joan Figueras:
Experimental Characterization of CMOS Interconnect Open Defects.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 123-136 (2008) |
| 2007 |
|---|
| 67 | EE | Daniel Arumí,
Rosa Rodríguez-Montañés,
Joan Figueras,
Stefan Eichenberger,
Camelia Hora,
Bram Kruseman,
Maurice Lousberg,
Ananta K. Majhi:
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages.
VTS 2007: 145-150 |
| 66 | EE | Rosa Rodríguez-Montañés,
Daniel Arumí,
Joan Figueras,
Stefan Eichenberger,
Camelia Hora,
Bram Kruseman,
Maurice Lousberg,
Ananta K. Majhi:
Diagnosis of Full Open Defects in Interconnecting Lines.
VTS 2007: 158-166 |
| 65 | EE | Salvador Manich,
L. Garcia-Deiros,
Joan Figueras:
Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2046-2058 (2007) |
| 2006 |
|---|
| 64 | | L. Balado,
E. Lupon,
L. García,
Rosa Rodríguez-Montañés,
Joan Figueras:
Lissajous Based Mixed-Signal Testing for N-Observable Signals.
DDECS 2006: 125-130 |
| 2005 |
|---|
| 63 | EE | R. Sanahuja,
V. Barcons,
L. Balado,
Joan Figueras:
Testing Biquad Filters under Parametric Shifts Using X-Y Zoning.
J. Electronic Testing 21(3): 257-265 (2005) |
| 2004 |
|---|
| 62 | EE | Salvador Manich,
L. García,
L. Balado,
E. Lupon,
Josep Rius,
Rosa Rodríguez-Montañés,
Joan Figueras:
BIST Technique by Equally Spaced Test Vector Sequences.
VTS 2004: 206-216 |
| 61 | EE | Rosa Rodríguez-Montañés,
D. Muñoz,
L. Balado,
Joan Figueras:
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours.
J. Electronic Testing 20(2): 143-153 (2004) |
| 60 | EE | Marcelino B. Santos,
Isabel C. Teixeira,
João Paulo Teixeira,
Salvador Manich,
L. Balado,
Joan Figueras:
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level.
J. Electronic Testing 20(4): 345-355 (2004) |
| 2003 |
|---|
| 59 | EE | Yves Bertrand,
Marie-Lise Flottes,
L. Balado,
Joan Figueras,
Anton Biasizzo,
Franc Novak,
Stefano Di Carlo,
Paolo Prinetto,
N. Pricopi,
Hans-Joachim Wunderlich,
J.-P. Van der Heyden:
Test Engineering Education in Europe: the EuNICE-Test Project.
MSE 2003: 85-86 |
| 2002 |
|---|
| 58 | EE | Rosa Rodríguez-Montañés,
D. Muñoz,
L. Balado,
Joan Figueras:
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours.
IOLTW 2002: 99-103 |
| 57 | EE | Marcelino B. Santos,
Isabel C. Teixeira,
João Paulo Teixeira,
Salvador Manich,
Rosa Rodríguez-Montañés,
Joan Figueras:
RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST.
ITC 2002: 814-823 |
| 56 | EE | Antoni Ferré,
Joan Figueras:
Leakage power bounds in CMOS digital technologies.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(6): 731-738 (2002) |
| 2001 |
|---|
| 55 | | Michel Renovell,
Penelope Faure,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
IS-FPGA : a new symmetric FPGA architecture with implicit scan.
ITC 2001: 924-931 |
| 54 | EE | Antonio Zenteno,
Víctor H. Champac,
Joan Figueras:
Detectability Conditions of Full Opens in the Interconnections.
J. Electronic Testing 17(2): 85-95 (2001) |
| 53 | EE | Paolo Prinetto,
Joan Figueras:
Guest Editorial.
J. Electronic Testing 17(3-4): 207 (2001) |
| 52 | EE | Antoni Ferré,
Joan Figueras:
LEAP: An Accurate Defect-Free IDDQ Estimator.
J. Electronic Testing 17(3-4): 267-274 (2001) |
| 51 | EE | Michel Renovell,
Jean Michel Portal,
Penelope Faure,
Joan Figueras,
Yervant Zorian:
A Discussion on Test Pattern Generation for FPGA - Implemented Circuits.
J. Electronic Testing 17(3-4): 283-290 (2001) |
| 50 | EE | Anna Maria Brosa,
Joan Figueras:
Digital Signature Proposal for Mixed-Signal Circuits.
J. Electronic Testing 17(5): 385-393 (2001) |
| 2000 |
|---|
| 49 | EE | Michel Renovell,
Jean Michel Portal,
Penelope Faure,
Joan Figueras,
Yervant Zorian:
TOF: a tool for test pattern generation optimization of an FPGA application oriented test.
Asian Test Symposium 2000: 323-328 |
| 48 | | Anna Maria Brosa,
Joan Figueras:
Digital signature proposal for mixed-signal circuits.
ITC 2000: 1041-1050 |
| 47 | EE | Salvador Manich,
A. Gabarró,
M. Lopez,
Joan Figueras,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
P. Teixeira,
M. Santos:
Low Power BIST by Filtering Non-Detecting Vectors.
J. Electronic Testing 16(3): 193-202 (2000) |
| 46 | EE | Anna Maria Brosa,
Joan Figueras:
On Maximizing the Coverage of Catastrophic and Parametric Faults.
J. Electronic Testing 16(3): 251-258 (2000) |
| 45 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family.
J. Electronic Testing 16(3): 289-299 (2000) |
| 44 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
Testing the Local Interconnect Resources of SRAM-Based FPGA's.
J. Electronic Testing 16(5): 513-520 (2000) |
| 1999 |
|---|
| 43 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
Minimizing the Number of Test Configurations for Different FPGA Families.
Asian Test Symposium 1999: 363-368 |
| 42 | EE | Josep Rius,
Joan Figueras:
Exploring the Combination of IDDQ and iDDt Testing: Energy Testing.
DATE 1999: 543-548 |
| 41 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's.
DATE 1999: 618-622 |
| 40 | EE | Anna Maria Brosa,
Joan Figueras:
On Optimizing Test Strategies for Analog Cells.
Great Lakes Symposium on VLSI 1999: 92-96 |
| 39 | EE | Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Joan Figueras,
Salvador Manich,
P. Teixeira,
M. Santos:
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.
ISCAS (1) 1999: 110-113 |
| 38 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
SRAM-Based FPGAs: Testing the Embedded RAM Modules.
J. Electronic Testing 14(1-2): 159-167 (1999) |
| 37 | EE | Anna Maria Brosa,
Joan Figueras:
Characterization of Floating Gate Defects in Analog Cells.
J. Electronic Testing 14(1-2): 23-31 (1999) |
| 36 | EE | Víctor H. Champac,
José Castillejos,
Joan Figueras:
IDDQ Testing of Opens in CMOS SRAMs.
J. Electronic Testing 15(1-2): 53-62 (1999) |
| 1998 |
|---|
| 35 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
SRAM-Based FPGA's: Testing the Interconnect/Logic Interface.
Asian Test Symposium 1998: 266-271 |
| 34 | EE | Rosa Rodríguez-Montañés,
Joan Figueras:
Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs.
DATE 1998: 490-494 |
| 33 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
RAM-Based FPGA's: A Test Approach for the Configurable Logic.
DATE 1998: 82-88 |
| 32 | EE | Cecilia Metra,
Michel Renovell,
G. Mojoli,
Jean Michel Portal,
Sandro Pastore,
Joan Figueras,
Yervant Zorian,
Davide Salvi,
Giacomo R. Sechi:
Novel Technique for Testing FPGAs.
DATE 1998: 89- |
| 31 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules.
FPL 1998: 139-148 |
| 30 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
SRAM-based FPGA's: testing the LUT/RAM modules.
ITC 1998: 1102-1111 |
| 29 | EE | Víctor H. Champac,
José Castillejos,
Joan Figueras:
IDDQ Testing of Opens in CMOS SRAMs.
VTS 1998: 106-111 |
| 28 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
Testing the Interconnect of RAM-Based FPGAs.
IEEE Design & Test of Computers 15(1): 45-50 (1998) |
| 27 | EE | Antoni Ferré,
Eugeni Isern,
Josep Rius,
Rosa Rodríguez-Montañés,
Joan Figueras:
IDDQ testing: state of the art and future trends.
Integration 26(1-2): 167-196 (1998) |
| 1997 |
|---|
| 26 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA.
Asian Test Symposium 1997: 254- |
| 25 | EE | Salvador Manich,
Joan Figueras:
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model.
ED&TC 1997: 597-602 |
| 24 | | Antoni Ferré,
Joan Figueras:
IDDQ Characterization in Submicron CMOS.
ITC 1997: 136-145 |
| 23 | EE | Michel Renovell,
Joan Figueras,
Yervant Zorian:
Test of RAM-based FPGA: methodology and application to the interconnect.
VTS 1997: 230-237 |
| 22 | EE | Vishwani D. Agrawal,
Robert C. Aitken,
J. Braden,
Joan Figueras,
S. Kumar,
Hans-Joachim Wunderlich,
Yervant Zorian:
Power Dissipation During Testing: Should We Worry About it?
VTS 1997: 456-457 |
| 21 | EE | Rosa Rodríguez-Montañés,
Joan Figueras:
Bridges in sequential CMOS circuits: current-voltage signatur.
VTS 1997: 68-73 |
| 20 | EE | Michael Nicolaidis,
Ricardo de Oliveira Duarte,
Salvador Manich,
Joan Figueras:
Fault-Secure Parity Prediction Arithmetic Operators.
IEEE Design & Test of Computers 14(2): 60-71 (1997) |
| 1996 |
|---|
| 19 | EE | Antoni Ferré,
Joan Figueras:
On estimating bounds of the quiescent current for I/sub DDQ/ testin.
VTS 1996: 106-111 |
| 18 | EE | Salvador Manich,
Michael Nicolaidis,
Joan Figueras:
Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring.
VTS 1996: 124-129 |
| 17 | EE | Rosa Rodríguez-Montañés,
E. M. J. G. Bruls,
Joan Figueras:
Bridging defects resistance in the metal layer of a CMOS process.
J. Electronic Testing 8(1): 35-46 (1996) |
| 16 | EE | Josep Rius,
Joan Figueras:
Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments.
J. Electronic Testing 9(3): 295-310 (1996) |
| 1995 |
|---|
| 15 | EE | Víctor H. Champac,
Joan Figueras:
Testability of floating gate defects in sequential circuits.
VTS 1995: 202-207 |
| 14 | EE | Josep Rius,
Joan Figueras:
Detecting I/sub DDQ/ defective CMOS circuits by depowering.
VTS 1995: 324-329 |
| 13 | EE | Eugeni Isern,
Joan Figueras:
IDDQ Test and Diagnosis of CMOS Circuits.
IEEE Design & Test of Computers 12(4): 60-67 (1995) |
| 12 | EE | Joan Figueras,
Michel Renovell:
Current testing in dynamic CMOS circuits.
J. Electronic Testing 6(1): 127-131 (1995) |
| 1994 |
|---|
| 11 | | Rosa Rodríguez-Montañés,
Joan Figueras:
Analysis of Bridging Defects in Sequential CMOS Circuits and their Current Testability.
EDAC-ETC-EUROASIC 1994: 356-360 |
| 10 | | Eugeni Isern,
Joan Figueras:
Test of Bridging Faults in Scan-based Sequential Circuits.
EDAC-ETC-EUROASIC 1994: 366-370 |
| 9 | EE | Víctor H. Champac,
Antonio Rubio,
Joan Figueras:
Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(3): 359-369 (1994) |
| 1993 |
|---|
| 8 | | Víctor H. Champac,
Antonio Rubio,
Joan Figueras:
Analysis of the Floating Gate Defect in CMOS.
DFT 1993: 101-108 |
| 7 | | Michel Renovell,
Joan Figueras:
Current Testing Viability in Dynamic CMOS Circuits.
DFT 1993: 207-214 |
| 6 | | Eugeni Isern,
Joan Figueras:
Test Generation with High Coverages for Quiescent Current Test of Bridging Faults in Combinational Circuits.
ITC 1993: 73-82 |
| 1992 |
|---|
| 5 | | Rosa Rodríguez-Montañés,
Joan Figueras,
Eric Bruls:
Bridging Defects Resistance Measurements in a CMOS Process.
ITC 1992: 892-899 |
| 4 | EE | J. A. Segura,
Víctor H. Champac,
Rosa Rodríguez-Montañés,
Joan Figueras,
J. A. Rubio:
Quiescent current analysis and experimentation of defective CMOS circuits.
J. Electronic Testing 3(4): 337-348 (1992) |
| 3 | EE | Josep Rius,
Joan Figueras:
Proportional BIC sensor for current testing.
J. Electronic Testing 3(4): 387-396 (1992) |
| 1991 |
|---|
| 2 | | Rosa Rodríguez-Montañés,
J. A. Segura,
Víctor H. Champac,
Joan Figueras,
J. A. Rubio:
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS.
ITC 1991: 510-519 |
| 1 | EE | Juan A. Carrasco,
Joan Figueras,
Annie Kuntzmann-Combelles:
Evaluation of safety-oriented two-version architectures.
Journal of Systems and Software 14(3): 155-162 (1991) |
