2008 |
30 | EE | Yi Wang,
Wai-Shing Luk,
Xuan Zeng,
Jun Tao,
Changhao Yan,
Jiarong Tong,
Wei Cai,
Jia Ni:
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays.
DAC 2008: 223-226 |
29 | EE | Yi Wang,
Xuan Zeng,
Jun Tao,
Hengliang Zhu,
Xu Luo,
Changhao Yan,
Wei Cai:
Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model.
ISQED 2008: 62-67 |
28 | EE | Qiang Fu,
Wai-Shing Luk,
Jun Tao,
Changhao Yan,
Xuan Zeng:
Characterizing Intra-Die Spatial Correlation Using Spectral Density Method.
ISQED 2008: 718-723 |
27 | EE | Yung-Ta Li,
Zhaojun Bai,
Yangfeng Su,
Xuan Zeng:
Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1571-1582 (2008) |
2007 |
26 | EE | Xuexin Liu,
Wai-Shing Luk,
Yu Song,
Pushan Tang,
Xuan Zeng:
Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic.
ASP-DAC 2007: 203-208 |
25 | EE | Peng Zhang,
Wai-Shing Luk,
Yu Song,
Jiarong Tong,
Pushan Tang,
Xuan Zeng:
WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design.
ASP-DAC 2007: 209-214 |
24 | EE | Jun Tao,
Xuan Zeng,
Wei Cai,
Yangfeng Su,
Dian Zhou,
Charles Chiang:
Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations.
ASP-DAC 2007: 474-479 |
23 | EE | Hengliang Zhu,
Xuan Zeng,
Wei Cai,
Jintao Xue,
Dian Zhou:
A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology.
DATE 2007: 1514-1519 |
22 | EE | Yung-Ta Li,
Zhaojun Bai,
Yangfeng Su,
Xuan Zeng:
Parameterized model order reduction via a two-directional Arnoldi process.
ICCAD 2007: 868-873 |
21 | EE | Fan Yang,
Xuan Zeng,
Yangfeng Su,
Dian Zhou:
RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect.
ISCAS 2007: 2710-2713 |
20 | EE | Ming-e Jing,
Yue Hao,
Dian Zhou,
Xuan Zeng:
A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1149-1155 (2007) |
2006 |
19 | EE | Hengliang Zhu,
Xuan Zeng,
Wei Cai,
Dian Zhou:
A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations.
APCCAS 2006: 1095-1098 |
18 | EE | Xuan Zeng,
Lihong Feng,
Yangfeng Su,
Wei Cai,
Dian Zhou,
Charles Chiang:
Time domain model order reduction by wavelet collocation method.
DATE 2006: 21-26 |
17 | EE | Jun Tao,
Xuan Zeng,
Fan Yang,
Yangfeng Su,
Lihong Feng,
Wei Cai,
Dian Zhou,
Charles Chiang:
A one-shot projection method for interconnects with process variations.
ISCAS 2006 |
2005 |
16 | EE | Bang Liu,
Xuan Zeng,
Yangfeng Su,
Jun Tao,
Zhaojun Bai,
Charles Chiang,
Dian Zhou:
Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits.
ASP-DAC 2005: 244-249 |
15 | EE | Xuan Zeng,
Bank Liu,
Jun Tao,
Charles Chiang,
Dian Zhou:
A novel wavelet method for noise analysis of nonlinear circuits.
ASP-DAC 2005: 471-476 |
14 | EE | Ruiming Li,
Dian Zhou,
Jin Liu,
Xuan Zeng:
Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires.
ISCAS (1) 2005: 113-116 |
13 | EE | Ruiming Li,
Dian Zhou,
Jin Liu,
Xuan Zeng:
Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1915-1924 (2005) |
2004 |
12 | EE | Jian Wang,
Jun Tao,
Xuan Zeng,
Charles Chiang,
Dian Zhou:
Analog circuit behavioral modeling via wavelet collocation method with auto-companding.
ASP-DAC 2004: 45-50 |
11 | EE | Lihong Feng,
Xuan Zeng,
Charles Chiang,
Dian Zhou,
Qiang Fang:
Direct Nonlinear Order Reduction with Variational Analysis.
DATE 2004: 1316-1321 |
10 | EE | Xin Zhou,
Dian Zhou,
Jin Liu,
Ruiming Li,
Xuan Zeng,
Charles Chiang:
Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method.
DATE 2004: 1322-1326 |
9 | EE | Yangfeng Su,
Jian Wang,
Xuan Zeng,
Zhaojun Bai,
Charles Chiang,
Dian Zhou:
SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits.
ICCAD 2004: 74-79 |
8 | | Lihong Feng,
Xuan Zeng,
Jiarong Tong,
Charles Chiang,
Dian Zhou:
Two-sided projection method in variational equation model order reduction of nonlinear circuits.
ISCAS (4) 2004: 816-819 |
7 | | Jian Wang,
Xuan Zeng,
Wei Cai,
Charles Chiang,
Jiarong Tong,
Dian Zhou:
Frequency domain wavelet method with GMRES for large-scale linear circuit simulation.
ISCAS (5) 2004: 321-324 |
2003 |
6 | EE | Ruiming Li,
Dian Zhou,
Jin Liu,
Xuan Zeng:
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing.
ICCAD 2003: 581-587 |
5 | EE | Xuan Zeng,
Jun Tao,
Yangfeng Su,
Wenbing Chen,
Dian Zhou:
An error distribution based nonlinear companding method for analog behavioral modeling via wavelet approximation.
ISCAS (3) 2003: 168-171 |
4 | EE | Xuan Zeng,
Sheng Huang,
Yangfeng Su,
Dian Zhou:
An efficient Sylvester equation solver for time domain circuit simulation by wavelet collocation method.
ISCAS (4) 2003: 664-667 |
2002 |
3 | EE | Xin Li,
Xuan Zeng,
Dian Zhou,
Xieting Ling:
Wavelet method for high-speed clock tree simulation.
ISCAS (1) 2002: 177-180 |
2001 |
2 | EE | Xin Li,
Xuan Zeng,
Dian Zhou,
Xieting Ling:
Behavioral Modeling of Analog Circuits by Wavelet Collocation Method.
ICCAD 2001: 65-69 |
1 | EE | Xin Li,
Bo Hu,
Xieting Ling,
Xuan Zeng:
A wavelet balance approach for steady-state analysis of nonlinear circuits.
ISCAS (3) 2001: 73-76 |