2009 | ||
---|---|---|
59 | EE | Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti, Yu Hu: Worst case timing jitter and amplitude noise in differential signaling. ISQED 2009: 40-46 |
58 | EE | Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He: Simultaneous test pattern compaction, ordering and X-filling for testing power reduction. ISQED 2009: 702-707 |
57 | EE | Yu Hu, Satyaki Das, Steven Trimberger, Lei He: Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate. IEEE Trans. on CAD of Integrated Circuits and Systems 28(4): 591-595 (2009) |
2008 | ||
56 | EE | Yu Hu, Xiang Fu, Xiaoxin Fan, Hideo Fujiwara: Localized random access scan: Towards low area and routing overhead. ASP-DAC 2008: 565-570 |
55 | EE | Fei Wang, Yu Hu, Huawei Li, Xiaowei Li: A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. ASP-DAC 2008: 571-576 |
54 | EE | Jia Li, Qiang Xu, Yu Hu, Xiaowei Li: On reducing both shift and capture power for scan-based testing. ASP-DAC 2008: 653-658 |
53 | EE | Xiang Fu, Huawei Li, Yu Hu, Xiaowei Li: Robust test generation for power supply noise induced path delay faults. ASP-DAC 2008: 659-662 |
52 | EE | Yu Hu, Victor Shih, Rupak Majumdar, Lei He: FPGA area reduction by multi-output function based sequential resynthesis. DAC 2008: 24-29 |
51 | EE | Jia Li, Qiang Xu, Yu Hu, Xiaowei Li: iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing. DATE 2008: 1184-1189 |
50 | EE | Fei Wang, Yu Hu, Xiaowei Li: Adaptive Diagnostic Pattern Generation for Scan Chains. DELTA 2008: 129-132 |
49 | EE | Jia Li, Qiang Xu, Yu Hu, Xiaowei Li: Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction. DELTA 2008: 26-31 |
48 | EE | Da Wang, Rui Li, Yu Hu, Huawei Li, Xiaowei Li: A Case Study on At-Speed Testing for a Gigahertz Microprocessor. DELTA 2008: 326-331 |
47 | EE | Hui Liu, Huawei Li, Yu Hu, Xiaowei Li: A Scan-Based Delay Test Method for Reduction of Overtesting. DELTA 2008: 521-526 |
46 | EE | Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, Qiang Xu: On capture power-aware test data compression for scan-based testing. ICCAD 2008: 67-72 |
45 | EE | Yu Hu, Zhe Feng, Lei He, Rupak Majumdar: Robust FPGA resynthesis based on fault-tolerant Boolean matching. ICCAD 2008: 706-713 |
44 | EE | Ying Zhang, Huawei Li, Xiaowei Li, Yu Hu: Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. VTS 2008: 377-382 |
43 | EE | Yu Hu, Yan Lin, Lei He, Tim Tuan: Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming. ACM Trans. Design Autom. Electr. Syst. 13(2): (2008) |
42 | EE | Yu Hu, Victor Shih, Rupak Majumdar, Lei He: Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1751-1760 (2008) |
41 | EE | Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, Xianlong Hong: Fashion: A Fast and Accurate Solution to Global Routing Problem. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 726-737 (2008) |
40 | EE | King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, Xinyi Zhang: Dual-Vdd Buffer Insertion for Power Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1498-1502 (2008) |
39 | EE | Tom Tong Jing, Yu Hu, Zhe Feng, Xian-Long Hong, Xiaodong Hu, Guiying Yan: A full-scale solution to the rectilinear obstacle-avoiding Steiner problem. Integration 41(3): 413-425 (2008) |
2007 | ||
38 | EE | Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong: DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ASP-DAC 2007: 256-261 |
37 | EE | Yu Hu, Satyaki Das, Steven Trimberger, Lei He: Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates. ICCAD 2007: 188-193 |
36 | EE | Yu Hu, Victor Shih, Rupak Majumdar, Lei He: Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping. ICCAD 2007: 350-353 |
35 | EE | Yu Hu, Qing Li, Siwei Ma, C. C. Jay Kuo: Decoder-Friendly Adaptive Deblocking Filter (DF-ADF) Mode Decision in H.264/AVC. ISCAS 2007: 3976-3979 |
34 | EE | Hao Yu, Yu Hu, Chunchen Liu, Lei He: Minimal skew clock embedding considering time variant temperature gradient. ISPD 2007: 173-180 |
33 | EE | Yu Hu, King Ho Tam, Tong Jing, Lei He: Fast dual-vdd buffering based on interconnect prediction and sampling. SLIP 2007: 95-102 |
32 | EE | Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra: Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. IEEE Trans. VLSI Syst. 15(5): 531-540 (2007) |
31 | EE | Tom Tong Jing, Zhe Feng, Yu Hu, Xian-Long Hong, Xiaodong Hu, Guiying Yan: lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) Complexity. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2073-2079 (2007) |
30 | EE | Wei Wang, Yu Hu, Yinhe Han, Xiaowei Li, You-Sheng Zhang: Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment. J. Comput. Sci. Technol. 22(5): 673-680 (2007) |
2006 | ||
29 | EE | Zhen Cao, Tong Jing, Yu Hu, Yiyu Shi, Xianlong Hong, Xiaodong Hu, Guiying Yan: DraXRouter: global routing in X-Architecture with dynamic resource assignment. ASP-DAC 2006: 618-623 |
28 | EE | Yu Hu, Yan Lin, Lei He, Tim Tuan: Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. DAC 2006: 478-483 |
27 | EE | Wei-Yang Lin, Kin-Chung Wong, Yu Hu, Nigel Boston: Face Recognition using 3D Summation Invariant Features. ICME 2006: 1733-1736 |
26 | EE | Yu Hu, Qing Li, Siwei Ma, C. C. Jay Kuo: Joint Rate-Distortion-Complexity Optimization for H.264 Motion Search. ICME 2006: 1949-1952 |
25 | EE | Yu Hu, Qing Li, Siwei Ma, C. C. Jay Kuo: Fast H.264/AVC Inter-Mode Decision with RDC Optimization. IIH-MSP 2006: 511-516 |
24 | EE | Jie Don, Yu Hu, Yinhe Han, Xiaowei Li: An on-chip combinational decompressor for reducing test data volume. ISCAS 2006 |
23 | EE | Yu Hu, Qiang Huo: An HMM Compensation Approach Using Unscented Transformation for Noisy Speech Recognition. ISCSLP 2006: 346-357 |
22 | EE | Yan Lin, Yu Hu, Lei He, Vijay Raghunat: An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. ISLPED 2006: 168-173 |
21 | EE | Zhe Feng, Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan: An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. ISPD 2006: 48-55 |
20 | EE | Yu Hu, Yinhe Han, Xiaowei Li, Huawei Li, Xiaoqing Wen: Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time. IEICE Transactions 89-D(10): 2616-2625 (2006) |
19 | EE | Yu Hu, Tong Jing, Zhe Feng, Xianlong Hong, Xiaodong Hu, Guiying Yan: ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm. J. Comput. Sci. Technol. 21(1): 147-152 (2006) |
2005 | ||
18 | EE | Zhen-Hua Ling, Yu Hu, Ren-Hua Wang: A Novel Source Analysis Method by Matching Spectral Characters of LF Model with STRAIGHT Spectrum. ACII 2005: 441-448 |
17 | EE | Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan: Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. ASAP 2005: 198-203 |
16 | EE | Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li: Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. ASP-DAC 2005: 53-58 |
15 | EE | Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng, Xiaodong Hu, Guiying Yan: An-OARSMan: obstacle-avoiding routing tree construction with good length performance. ASP-DAC 2005: 7-12 |
14 | EE | Yinhe Han, Xiaowei Li, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra: Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor. Asian Test Symposium 2005: 372-377 |
13 | EE | Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li: Using MUXs Network to Hide Bunches of Scan Chains. ISQED 2005: 238-243 |
12 | EE | Yu Hu, Xiaowei Li, Huawei Li, Xiaoqing Wen: Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. PRDC 2005: 175-182 |
11 | EE | Yu Hu, Qing Li, C. C. Jay Kuo: Run-Time Power Consumption Modeling for Embedded Multimedia Systems. RTCSA 2005: 353-356 |
10 | EE | Yu Hu, Tong Jing, Xianlong Hong, Xiaodong Hu, Guiying Yan: A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. SAMOS 2005: 344-353 |
9 | EE | Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, Xiaoqing Wen: Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores. IEICE Transactions 88-D(9): 2126-2134 (2005) |
2004 | ||
8 | EE | Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li: Pair Balance-Based Test Scheduling for SOCs. Asian Test Symposium 2004: 236-241 |
7 | EE | Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra: Rapid and Energy-Efficient Testing for Embedded Cores. Asian Test Symposium 2004: 8-13 |
6 | EE | Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra: Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. DFT 2004: 298-305 |
5 | Yu Hu, Qing Li, C. C. Jay Kuo: Efficient implementation of elliptic curve cryptography (ECC) on VLIW-micro-architecture media processor. ICME 2004: 879-882 | |
2003 | ||
4 | EE | Gary S. H. Tan, Yu Hu, Farshad Moradi: Automatic SOM Compatibility Check and FOM Development. DS-RT 2003: 60-67 |
3 | Yong Zhao, Yu Hu: GRESS - a Grid Replica Selection Service. ISCA PDCS 2003: 423-429 | |
2000 | ||
2 | EE | Ren-Hua Wang, Qingfeng Liu, Yu Hu, Bo Yin, Xiaoru Wu: KD2000 Chinese Text-To-Speech System. ICMI 2000: 300-307 |
1996 | ||
1 | EE | Yu Hu, S. Lennart Johnsson: Implementing O(N) N-Body Algorithms Efficiently in Data-Parallel Languages. Scientific Programming 5(4): 337-364 (1996) |