| 2007 |
|---|
| 10 | EE | Chang Woo Kang,
Ali Iranli,
Massoud Pedram:
A Synthesis Approach for Coarse-Grained Antifuse-Based FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1564-1575 (2007) |
| 2006 |
|---|
| 9 | EE | Chang Woo Kang,
Massoud Pedram:
Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs.
ACM Great Lakes Symposium on VLSI 2006: 79-84 |
| 8 | EE | Chanseok Hwang,
Chang Woo Kang,
Massoud Pedram:
Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs.
ISQED 2006: 741-746 |
| 2005 |
|---|
| 7 | EE | Chang Woo Kang,
Massoud Pedram:
Clustering techniques for coarse-grained, antifuse FPGAs.
ASP-DAC 2005: 785-790 |
| 6 | EE | Chang Woo Kang,
Massoud Pedram:
A Leakage-aware Low Power Technology Mapping Algorithm Considering the Hot-Carrier Effect.
J. Low Power Electronics 1(2): 133-144 (2005) |
| 5 | EE | Jaffrey Draper,
Tim Barrett,
Jeff Sondeen,
Sumit D. Mediratta,
Chang Woo Kang,
Ihn Kim,
Gokhan Daglikoca:
A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System.
VLSI Signal Processing 40(1): 73-84 (2005) |
| 2004 |
|---|
| 4 | EE | Chang Woo Kang,
Ali Iranli,
Massoud Pedram:
Technology mapping and packing for coarse-grained, anti-fuse based FPGAs.
ASP-DAC 2004: 209-211 |
| 2003 |
|---|
| 3 | EE | Chang Woo Kang,
Soroush Abbaspour,
Massoud Pedram:
Buffer sizing for minimum energy-delay product by using an approximating polynomial.
ACM Great Lakes Symposium on VLSI 2003: 112-115 |
| 2002 |
|---|
| 2 | EE | Jeffrey T. Draper,
Jacqueline Chame,
Mary W. Hall,
Craig S. Steele,
Tim Barrett,
Jeff LaCoss,
John J. Granacki,
Jaewook Shin,
Chun Chen,
Chang Woo Kang,
Ihn Kim Gokhan:
The architecture of the DIVA processing-in-memory chip.
ICS 2002: 14-25 |
| 1 | | Chang Woo Kang,
Massoud Pedram:
Technology Mapping for Low Leakage Power with Hot-Carrier Effect Consideration.
IWLS 2002: 295-300 |
