| 2009 |
|---|
| 48 | EE | Andrew DeOrio,
Ilya Wagner,
Valeria Bertacco:
Dacota: Post-silicon validation of the memory subsystem in multi-core designs.
HPCA 2009: 405-416 |
| 2008 |
|---|
| 47 | EE | Stephen Plaza,
Igor L. Markov,
Valeria Bertacco:
Random Stimulus Generation using Entropy and XOR Constraints.
DATE 2008: 664-669 |
| 46 | EE | Ilya Wagner,
Valeria Bertacco:
MCjammer: Adaptive Verification for Multi-core Designs.
DATE 2008: 670-675 |
| 45 | EE | Ilya Wagner,
Valeria Bertacco:
Reversi: Post-silicon validation system for modern microprocessors.
ICCD 2008: 307-314 |
| 44 | EE | Andrew DeOrio,
Adam Bauserman,
Valeria Bertacco:
Post-silicon verification for cache coherence.
ICCD 2008: 348-355 |
| 43 | EE | Andrea Pellegrini,
Kypros Constantinides,
Dan Zhang,
Shobana Sudhakar,
Valeria Bertacco,
Todd M. Austin:
CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework.
ICCD 2008: 363-370 |
| 42 | EE | Kai-Hui Chang,
Igor L. Markov,
Valeria Bertacco:
Reap what you sow: spare cells for post-silicon metal fix.
ISPD 2008: 103-110 |
| 41 | EE | Stephen Plaza,
Igor L. Markov,
Valeria Bertacco:
Optimizing non-monotonic interconnect using functional simulation and logic restructuring.
ISPD 2008: 95-102 |
| 40 | EE | Joseph L. Greathouse,
Ilya Wagner,
David A. Ramos,
Gautam Bhatnagar,
Todd M. Austin,
Valeria Bertacco,
Seth Pettie:
Testudo: Heavyweight security analysis via statistical sampling.
MICRO 2008: 117-128 |
| 39 | EE | Kai-Hui Chang,
Igor L. Markov,
Valeria Bertacco:
Fixing Design Errors With Counterexamples and Resynthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 184-188 (2008) |
| 38 | EE | Stephen Plaza,
Igor L. Markov,
Valeria Bertacco:
Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2107-2119 (2008) |
| 37 | EE | Ilya Wagner,
Valeria Bertacco,
Todd M. Austin:
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 380-393 (2008) |
| 36 | EE | Kai-Hui Chang,
Igor L. Markov,
Valeria Bertacco:
SafeResynth: A new technique for physical synthesis.
Integration 41(4): 544-556 (2008) |
| 2007 |
|---|
| 35 | EE | Stephen Plaza,
Kai-Hui Chang,
Igor L. Markov,
Valeria Bertacco:
Node Mergers in the Presence of Don't Cares.
ASP-DAC 2007: 414-419 |
| 34 | EE | Kai-Hui Chang,
Igor L. Markov,
Valeria Bertacco:
Safe Delay Optimization for Physical Synthesis.
ASP-DAC 2007: 628-633 |
| 33 | EE | Kai-Hui Chang,
Igor L. Markov,
Valeria Bertacco:
Fixing Design Errors with Counterexamples and Resynthesis.
ASP-DAC 2007: 944-949 |
| 32 | EE | Mojtaba Mehrara,
Mona Attariyan,
Smitha Shyam,
Kypros Constantinides,
Valeria Bertacco,
Todd M. Austin:
Low-cost protection for SER upsets and silicon defects.
DATE 2007: 1146-1151 |
| 31 | EE | Ilya Wagner,
Valeria Bertacco:
Engineering trust with semantic guardians.
DATE 2007: 743-748 |
| 30 | EE | Kai-Hui Chang,
Igor L. Markov,
Valeria Bertacco:
Automating post-silicon debugging and repair.
ICCAD 2007: 91-98 |
| 29 | EE | Kai-Hui Chang,
David A. Papa,
Igor L. Markov,
Valeria Bertacco:
InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization.
ISQED 2007: 487-494 |
| 28 | EE | Kypros Constantinides,
Onur Mutlu,
Todd M. Austin,
Valeria Bertacco:
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation.
MICRO 2007: 97-108 |
| 27 | EE | Andrew DeOrio,
Adam Bauserman,
Valeria Bertacco:
Chico: An On-chip Hardware Checker for Pipeline Control Logic.
MTV 2007: 91-97 |
| 26 | EE | Kai-Hui Chang,
Igor L. Markov,
Valeria Bertacco:
Postplacement rewiring by exhaustive search for functional symmetries.
ACM Trans. Design Autom. Electr. Syst. 12(3): (2007) |
| 25 | EE | Kai-Hui Chang,
Valeria Bertacco,
Igor L. Markov:
Simulation-Based Bug Trace Minimization With BMC-Based Refinement.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 152-165 (2007) |
| 24 | EE | Ilya Wagner,
Valeria Bertacco,
Todd M. Austin:
Microprocessor Verification via Feedback-Adjusted Markov Models.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1126-1138 (2007) |
| 23 | EE | Kypros Constantinides,
Stephen Plaza,
Jason A. Blome,
Valeria Bertacco,
Scott A. Mahlke,
Todd M. Austin,
Bin Zhang,
Michael Orshansky:
Architecting a reliable CMP switch architecture.
TACO 4(1): (2007) |
| 2006 |
|---|
| 22 | EE | Ilya Wagner,
Valeria Bertacco,
Todd M. Austin:
Depth-driven verification of simultaneous interfaces.
ASP-DAC 2006: 442-447 |
| 21 | EE | Smitha Shyam,
Kypros Constantinides,
Sujay Phadke,
Valeria Bertacco,
Todd M. Austin:
Ultra low-cost defect protection for microprocessor pipelines.
ASPLOS 2006: 73-82 |
| 20 | EE | Ilya Wagner,
Valeria Bertacco,
Todd M. Austin:
Shielding against design flaws with field repairable control logic.
DAC 2006: 344-347 |
| 19 | EE | Smitha Shyam,
Valeria Bertacco:
Distance-guided hybrid verification with GUIDO.
DATE 2006: 1211-1216 |
| 18 | EE | Kypros Constantinides,
Stephen Plaza,
Jason A. Blome,
Bin Zhang,
Valeria Bertacco,
Scott A. Mahlke,
Todd M. Austin,
Michael Orshansky:
BulletProof: a defect-tolerant CMP switch architecture.
HPCA 2006: 5-16 |
| 17 | EE | Beth Isaksen,
Valeria Bertacco:
Verification through the principle of least astonishment.
ICCAD 2006: 860-867 |
| 16 | EE | Valeria Bertacco:
Low maintenance verification.
SBCCI 2006: 12 |
| 15 | EE | Valeria Bertacco:
Formal verification for real-world designs.
SBCCI 2006: 5 |
| 2005 |
|---|
| 14 | EE | Todd M. Austin,
Valeria Bertacco,
David Blaauw,
Trevor N. Mudge:
Opportunities and challenges for better than worst-case design.
ASP-DAC 2005: 2-7 |
| 13 | EE | Stephen Plaza,
Valeria Bertacco:
STACCATO: disjoint support decompositions from BDDs through symbolic kernels.
ASP-DAC 2005: 276-279 |
| 12 | EE | Ilya Wagner,
Valeria Bertacco,
Todd M. Austin:
StressTest: an automatic approach to test generation via activity monitors.
DAC 2005: 783-788 |
| 11 | | Kai-Hui Chang,
Valeria Bertacco,
Igor L. Markov:
Simulation-based bug trace minimization with BMC-based refinement.
ICCAD 2005: 1045-1051 |
| 10 | | Kai-Hui Chang,
Igor L. Markov,
Valeria Bertacco:
Post-placement rewiring and rebuffering by exhaustive search for functional symmetries.
ICCAD 2005: 56-63 |
| 9 | EE | Todd M. Austin,
Valeria Bertacco:
Deployment of Better Than Worst-Case Design: Solutions and Needs.
ICCD 2005: 550-558 |
| 2004 |
|---|
| 8 | EE | Seokwoo Lee,
Shidhartha Das,
Valeria Bertacco,
Todd M. Austin,
David Blaauw,
Trevor N. Mudge:
Circuit-aware architectural simulation.
DAC 2004: 305-310 |
| 7 | EE | Nam Sung Kim,
Taeho Kgil,
Valeria Bertacco,
Todd M. Austin,
Trevor N. Mudge:
Microarchitectural power modeling techniques for deep sub-micron microprocessors.
ISLPED 2004: 212-217 |
| 2002 |
|---|
| 6 | EE | Valeria Bertacco,
Kunle Olukotun:
Efficient state representation for symbolic simulation.
DAC 2002: 99-104 |
| 2000 |
|---|
| 5 | | Pei-Hsin Ho,
Thomas R. Shiple,
Kevin Harer,
James H. Kukula,
Robert F. Damiano,
Valeria Bertacco,
Jerry Taylor,
Jiang Long:
Smart Simulation Using Collaborative Formal and Simulation Engines.
ICCAD 2000: 120-126 |
| 1999 |
|---|
| 4 | EE | Valeria Bertacco,
Maurizio Damiani,
Stefano Quer:
Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits.
DAC 1999: 391-396 |
| 1997 |
|---|
| 3 | EE | Valeria Bertacco,
Maurizio Damiani:
The disjunctive decomposition of logic functions.
ICCAD 1997: 78-82 |
| 1996 |
|---|
| 2 | EE | Valeria Bertacco,
Maurizio Damiani:
Boolean Function Representation Using Parallel-Access Diagrams.
Great Lakes Symposium on VLSI 1996: 112-117 |
| 1 | EE | Valeria Bertacco,
Maurizio Damiani:
Boolean Function Representation Based on Disjoint-Support Decompositions.
ICCD 1996: 27- |
