| 2007 |
|---|
| 5 | EE | Lili Zhou,
Cherry Wakayama,
Robin Panda,
Nuttorn Jangkrajarng,
Bo Hu,
C.-J. Richard Shi:
Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits.
ICCD 2007: 194-201 |
| 4 | EE | Ming Su,
Lili Zhou,
C.-J. Richard Shi:
Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining.
ICCD 2007: 636-643 |
| 3 | EE | Lili Zhou,
Cherry Wakayama,
C.-J. Richard Shi:
CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1270-1282 (2007) |
| 2006 |
|---|
| 2 | EE | Lili Zhou,
Cherry Wakayama,
Nuttorn Jangkrajarng,
Bo Hu,
C.-J. Richard Shi:
A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits.
ASP-DAC 2006: 92-93 |
| 2005 |
|---|
| 1 | EE | Bo Hu,
Zhao Li,
Lili Zhou,
C.-J. Richard Shi,
Kwang-Hyun Baek,
Myung-Jun Choe:
Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC.
ISCAS (6) 2005: 5621-5624 |
