| 2008 |
|---|
| 9 | EE | Igor Keller,
King Ho Tam,
Vinod Kariat:
Challenges in gate level modeling for delay and SI at 65nm and below.
DAC 2008: 468-473 |
| 8 | EE | King Ho Tam,
Yu Hu,
Lei He,
Tom Tong Jing,
Xinyi Zhang:
Dual-Vdd Buffer Insertion for Power Reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1498-1502 (2008) |
| 2007 |
|---|
| 7 | EE | Yu Hu,
King Ho Tam,
Tong Jing,
Lei He:
Fast dual-vdd buffering based on interconnect prediction and sampling.
SLIP 2007: 95-102 |
| 6 | EE | Lei He,
Andrew B. Kahng,
King Ho Tam,
Jinjun Xiong:
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 845-857 (2007) |
| 2005 |
|---|
| 5 | EE | King Ho Tam,
Lei He:
Power optimal dual-Vdd buffered tree considering buffer stations and blockages.
DAC 2005: 497-502 |
| 4 | EE | Jinjun Xiong,
King Ho Tam,
Lei He:
Buffer Insertion Considering Process Variation.
DATE 2005: 970-975 |
| 3 | EE | Yu Ching Chang,
King Ho Tam,
Lei He:
Power-optimal repeater insertion considering Vdd and Vth as design freedoms.
ISLPED 2005: 137-142 |
| 2 | EE | Lei He,
Andrew B. Kahng,
King Ho Tam,
Jinjun Xiong:
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation.
ISPD 2005: 78-85 |
| 2004 |
|---|
| 1 | EE | Lucanus J. Simonson,
King Ho Tam,
Nataraj Akkiraju,
Mosur Mohan,
Lei He:
Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction.
ISQED 2004: 69-74 |
