| 2008 |
|---|
| 23 | EE | Hidenori Ohta,
Toshinori Yamada,
Chikaaki Kodama,
Kunihiro Fujiyoshi:
The O-Sequence: Representation of 3D-Dissection.
IEICE Transactions 91-A(8): 2111-2119 (2008) |
| 2007 |
|---|
| 22 | EE | Kunihiro Fujiyoshi,
Hidenori Kawai,
Keisuke Ishihara:
DTS: A Tree Based Representation for 3D-Block Packing.
ISCAS 2007: 1045-1048 |
| 21 | EE | Shinichi Koda,
Chikaaki Kodama,
Kunihiro Fujiyoshi:
Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 659-668 (2007) |
| 20 | EE | Kunihiro Fujiyoshi,
Chikaaki Kodama,
Akira Ikeda:
A fast algorithm for rectilinear block packing based on selected sequence-pair.
Integration 40(3): 274-284 (2007) |
| 2006 |
|---|
| 19 | EE | N. Okada,
Chikaaki Kodama,
T. Sato,
Kunihiro Fujiyoshi:
Thermal Driven Module Placement Using Sequence-pair.
APCCAS 2006: 1871-1874 |
| 18 | EE | Y. Kohira,
Chikaaki Kodama,
Kunihiro Fujiyoshi,
A. Takahashi:
Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems.
ISCAS 2006 |
| 17 | EE | Shinichi Kouda,
Chikaaki Kodama,
Kunihiro Fujiyoshi:
Improved method of cell placement with symmetry constraints for analog IC layout design.
ISPD 2006: 192-199 |
| 2005 |
|---|
| 16 | EE | Hiroaki Itoga,
Chikaaki Kodama,
Kunihiro Fujiyoshi:
A Graph Based Soft Module Handling in Floorplan.
IEICE Transactions 88-A(12): 3390-3397 (2005) |
| 15 | EE | Chikaaki Kodama,
Kunihiro Fujiyoshi:
Minimizing the Number of Empty Rooms on Floorplan by Dissection Line Merge.
IEICE Transactions 88-D(7): 1389-1396 (2005) |
| 2004 |
|---|
| 14 | | Chikaaki Kodama,
Kunihiro Fujiyoshi,
Teppei Koga:
A novel encoding method into sequence-pair.
ISCAS (5) 2004: 329-332 |
| 2002 |
|---|
| 13 | EE | H. Saito,
K. Wakata,
Kunihiro Fujiyoshi,
K. Sakanushi,
T. Obata:
An improved method of convex-shaped block packing based on sequence-pair [VLSI layout].
APCCAS (2) 2002: 125-130 |
| 12 | EE | Chikaaki Kodama,
Kunihiro Fujiyoshi:
An efficient decoding method of sequence-pair.
APCCAS (2) 2002: 131-136 |
| 2000 |
|---|
| 11 | EE | Kunihiro Fujiyoshi,
Hiroshi Murata:
Arbitrary convex and concave rectilinear block packing usingsequence-pair.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 224-233 (2000) |
| 1999 |
|---|
| 10 | EE | Kunihiro Fujiyoshi,
Hiroshi Murata:
Arbitrary convex and concave rectilinear block packing using sequence-pair.
ISPD 1999: 103-110 |
| 1998 |
|---|
| 9 | EE | Hiroshi Murata,
Kunihiro Fujiyoshi,
Mineo Kaneko:
VLSI/PCB placement with obstacles based on sequence pair.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 60-68 (1998) |
| 8 | EE | Shigetoshi Nakatake,
Kunihiro Fujiyoshi,
Hiroshi Murata,
Yoji Kajitani:
Module packing based on the BSG-structure and IC layout applications.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 519-530 (1998) |
| 1997 |
|---|
| 7 | EE | Hiroshi Murata,
Kunihiro Fujiyoshi,
Mineo Kaneko:
VLSI/PCB placement with obstacles based on sequence-pair.
ISPD 1997: 26-31 |
| 6 | EE | Kunihiro Fujiyoshi,
Yoji Kajitani,
Hiroshi Niitsu:
Design of minimum and uniform bipartites for optimum connection blocks of FPGA.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1377-1383 (1997) |
| 1996 |
|---|
| 5 | EE | Shigetoshi Nakatake,
Kunihiro Fujiyoshi,
Hiroshi Murata,
Yoji Kajitani:
Module placement on BSG-structure and IC layout applications.
ICCAD 1996: 484-491 |
| 4 | EE | Hiroshi Murata,
Kunihiro Fujiyoshi,
Shigetoshi Nakatake,
Yoji Kajitani:
VLSI module placement based on rectangle-packing by the sequence-pair.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1518-1524 (1996) |
| 1995 |
|---|
| 3 | EE | Hiroshi Murata,
Kunihiro Fujiyoshi,
Shigetoshi Nakatake,
Yoji Kajitani:
Rectangle-packing-based module placement.
ICCAD 1995: 472-479 |
| 1994 |
|---|
| 2 | | Kunihiro Fujiyoshi,
Yoji Kajitani,
Hiroshi Niitsu:
The Totally-Perfect Bipartite Graph and Its Construction.
ISAAC 1994: 541-549 |
| 1 | | Kunihiro Fujiyoshi,
Yoji Kajitani,
Hiroshi Niitsu:
Design of Optimum Totally Perfect Connection-Blocks of FPGA.
ISCAS 1994: 221-224 |
