Srinivasan Murali

2008
25	EE	Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen Boyd, Luca Benini, Giovanni De Micheli: Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization. DATE 2008: 110-115
24	EE	David Atienza, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Luca Benini, Giovanni De Micheli: Network-on-Chip design and synthesis outlook. Integration 41(3): 340-359 (2008)
2007
23	EE	Srinivasan Murali, Almir Mutapcic, David Atienza, Rajesh Gupta, Stephen Boyd, Giovanni De Micheli: Temperature-aware processor frequency assignment for MPSoCs using convex optimization. CODES+ISSS 2007: 111-116
22	EE	Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini: NoC Design and Implementation in 65nm Technology. NOCS 2007: 273-282
21	EE	Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli: Early wire characterization for predictable network-on-chip global interconnects. SLIP 2007: 57-64
20	EE	Srinivasan Murali, Giovanni De Micheli: An Application-Specific Design Methodology for STbus Crossbar Generation CoRR abs/0710.4671: (2007)
19	EE	Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini: Bringing NoCs to 65 nm. IEEE Micro 27(5): 75-85 (2007)
18	EE	Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo: Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. IEEE Trans. VLSI Syst. 15(8): 869-880 (2007)
17	EE	Srinivasan Murali, Luca Benini, Giovanni De Micheli: An Application-Specific Design Methodology for On-Chip Crossbar Generation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1283-1296 (2007)
16	EE	Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli: Timing-Error-Tolerant Network-on-Chip Design Methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1297-1310 (2007)
2006
15	EE	Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli: Mapping and configuration methods for multi-use-case networks on chips. ASP-DAC 2006: 146-151
14	EE	Martijn Coenen, Srinivasan Murali, Andrei Radulescu, Kees Goossens, Giovanni De Micheli: A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control. CODES+ISSS 2006: 130-135
13	EE	Srinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli: A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip. DAC 2006: 845-848
12	EE	Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli: A methodology for mapping multiple use-cases onto networks on chips. DATE 2006: 118-123
11	EE	Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo: Designing application-specific networks on chips with floorplan information. ICCAD 2006: 355-362
10	EE	Federico Angiolini, David Atienza, Srinivasan Murali, Luca Benini, Giovanni De Micheli: Reliability Support for On-Chip Memories Using Networks-on-Chip. ICCD 2006
9	EE	Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo: Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. VLSI-SoC 2006: 158-163
2005
8	EE	Srinivasan Murali, Luca Benini, Giovanni De Micheli: Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees. ASP-DAC 2005: 27-32
7	EE	Rutuparna Tamhankar, Srinivasan Murali, Giovanni De Micheli: Performance driven reliable link design for networks on chips. ASP-DAC 2005: 749-754
6	EE	Srinivasan Murali, Giovanni De Micheli: An Application-Specific Design Methodology for STbus Crossbar Generation. DATE 2005: 1176-1181
5	EE	Srinivasan Murali, Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli: Analysis of Error Recovery Schemes for Networks on Chips. IEEE Design & Test of Computers 22(5): 434-442 (2005)
4	EE	Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini, Giovanni De Micheli: NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. IEEE Trans. Parallel Distrib. Syst. 16(2): 113-129 (2005)
2004
3	EE	Srinivasan Murali, Giovanni De Micheli: SUNMAP: a tool for automatic topology selection and generation for NoCs. DAC 2004: 914-919
2	EE	Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli: ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip. DATE 2004: 884-889
1	EE	Srinivasan Murali, Giovanni De Micheli: Bandwidth-Constrained Mapping of Cores onto NoC Architectures. DATE 2004: 896-903

Coauthor Index

1	Federico Angiolini	[9] [10] [11] [16] [19] [22] [24]
2	David Atienza	[9] [10] [11] [13] [18] [19] [21] [22] [23] [24] [25]
3	Stéphane Badel	[21]
4	Luca Benini	[2] [4] [5] [8] [9] [10] [11] [13] [16] [17] [18] [19] [22] [24] [25]
5	Davide Bertozzi	[4]
6	Stephen Boyd	[23] [25]
7	Salvatore Carta	[9] [11] [18]
8	Martijn Coenen	[12] [14] [15]
9	Kees G. W. Goossens (Kees Goossens)	[12] [14] [15]
10	Rajesh K. Gupta (Rajesh Gupta)	[23] [25]
11	Ilhan Hatirnaz	[21]
12	Mary Jane Irwin	[5]
13	Antoine Jalabert	[2] [4]
14	Yusuf Leblebici	[21]
15	Paolo Meloni	[9] [11] [18] [22]
16	Giovanni De Micheli	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25]
17	Almir Mutapcic	[23] [25]
18	Nuria Pazos	[21]
19	Antonio Pullini	[16] [19] [22] [24]
20	Andrei Radulescu	[12] [14] [15]
21	Luigi Raffo	[9] [11] [18] [22]
22	Stergios Stergiou	[4] [16]
23	Rutuparna Tamhankar	[4] [7] [16]
24	Theo Theocharides	[5]
25	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[5]