Navakanta Bhat

2008
15	EE	Rakesh Gnana David Jeyasingh, Navakanta Bhat: A low power, process invariant keeper for high speed dynamic logic circuits. ISCAS 2008: 1668-1671
14	EE	Kannan Aryaperumal Sankaragomathi, Manodipan Sahoo, Satyam Dwivedi, Bharadwaj S. Amrutur, Navakanta Bhat: Optimal power and noise allocation for analog and digital sections of a low power radio receiver. ISLPED 2008: 271-276
13	EE	Sukumar Jairam, Navakanta Bhat: GyroCompiler: A Soft IP Model Synthesis and Analysis Framework for Design of MEMS Based Gyroscopes. VLSI Design 2008: 589-594
2007
12	EE	B. P. Harish, Navakanta Bhat, Mahesh B. Patil: Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs. ICCTA 2007: 94-98
11	EE	Balaji Jayaraman, Navakanta Bhat: High Precision 16-bit Readout Gas Sensor Interface in 0.13µm CMOS. ISCAS 2007: 3071-3074
10	EE	Srimoyee Sen, Urmimala Roy, Chaitanya Kshirsagar, Navakanta Bhat, Chandan Kumar Sarkar: Circuit prospects of DGFET: Variable gain differential amplifier an a schmitt trigger with adjustable hysteresis. VLSI-SoC 2007: 280-283
9	EE	B. P. Harish, Navakanta Bhat, Mahesh B. Patil: On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 606-614 (2007)
2005
8	EE	R. Srinivasan, Navakanta Bhat: Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications. VLSI Design 2005: 392-396
2004
7	EE	H. C. Srinivasaiah, Navakanta Bhat: Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment. VLSI Design 2004: 285-290
6	EE	Sukumar Jairam, C. Venkatesh, Navakanta Bhat, Shyam Singh, Rudra Pratap: A Quasi Static Model for a Simply Supported Beam in a Circuit Simulation Framework. VLSI Design 2004: 642-645
2003
5	EE	R. Srinivasan, Navakanta Bhat: Effect of Scaling on the Non-quasi-static Behaviour of the MOSFET for RF IC's. VLSI Design 2003: 105-109
4	EE	H. C. Srinivasaiah, Navakanta Bhat: Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 742-747 (2003)
3	EE	C. Venkatesh, Shashidhar Pati, Navakanta Bhat: Torsional Mems Varactor With Low Actuation Voltage. International Journal of Computational Engineering Science 4(3): 555-558 (2003)
2	EE	Shashidhar Pati, C. Venkatesh, Navakanta Bhat, Rudra Pratap: Voltage Controlled Oscillator Using Tunable Mems Resonator. International Journal of Computational Engineering Science 4(3): 675-678 (2003)
2002
1	EE	H. C. Srinivasaiah, Navakanta Bhat: Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay. VLSI Design 2002: 225-

Coauthor Index

1	Bharadwaj S. Amrutur	[14]
2	Satyam Dwivedi	[14]
3	B. P. Harish	[9] [12]
4	Sukumar Jairam	[6] [13]
5	Balaji Jayaraman	[11]
6	Rakesh Gnana David Jeyasingh	[15]
7	Chaitanya Kshirsagar	[10]
8	Shashidhar Pati	[2] [3]
9	Mahesh B. Patil	[9] [12]
10	Rudra Pratap	[2] [6]
11	Urmimala Roy	[10]
12	Manodipan Sahoo	[14]
13	Kannan Aryaperumal Sankaragomathi	[14]
14	Chandan Kumar Sarkar	[10]
15	Srimoyee Sen	[10]
16	Shyam Singh	[6]
17	H. C. Srinivasaiah	[1] [4] [7]
18	R. Srinivasan	[5] [8]
19	C. Venkatesh	[2] [3] [6]

Colors in the list of coauthors