Peter Ramyalal Suaris
List of publications from the DBLP Bibliography Server - FAQ
2007 | ||
---|---|---|
15 | EE | Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng: Efficient Timing Analysis With Known False Paths Using Biclique Covering. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 959-969 (2007) |
2005 | ||
14 | EE | Peter Suaris, Dongsheng Wang, Nan-Chi Chou: A practical cut-based physical retiming algorithm for field programmable gate arrays. ASP-DAC 2005: 1027-1030 |
13 | EE | Yuzheng Ding, Peter Suaris, Nan-Chi Chou: The effect of post-layout pin permutation on timing. FPGA 2005: 41-50 |
12 | Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris: Improving the efficiency of static timing analysis with false paths. ICCAD 2005: 527-531 | |
11 | Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge: Total power-optimal pipelining and parallel processing under process variations in nanometer technology. ICCAD 2005: 535-540 | |
10 | EE | Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris: Unified quadratic programming approach for mixed mode placement. ISPD 2005: 193-199 |
2004 | ||
9 | EE | Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris: Fast adders in modern FPGAs. FPGA 2004: 250 |
8 | EE | Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou: Incremental physical resynthesis for timing optimization. FPGA 2004: 99-108 |
2003 | ||
7 | EE | Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu: An algebraic multigrid solver for analytical placement with layout based clustering. DAC 2003: 794-799 |
6 | EE | Peter Suaris, Dongsheng Wang, Pei-Ning Guo, Nan-Chi Chou: A physical retiming algorithm for field programmable gate arrays. FPGA 2003: 247 |
5 | EE | Dongsheng Wang, Peter Suaris, Nan-Chi Chou: A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages. PATMOS 2003: 511-519 |
2000 | ||
4 | EE | Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska: Fast post-placement rewiring using easily detectable functional symmetries. DAC 2000: 286-289 |
1997 | ||
3 | EE | Ajay J. Daga, Peter Suaris: Interface Timing Verification Drives System Design. DAC 1997: 240-245 |
1994 | ||
2 | EE | Lalgudi N. Kannan, Peter Suaris, Hong-Gee Fang: A Methodology and Algorithms for Post-Placement Delay Optimization. DAC 1994: 327-332 |
1989 | ||
1 | EE | Peter Ramyalal Suaris, Gershon Kedem: A quadrisection-based combined place and route scheme for standard cells. IEEE Trans. on CAD of Integrated Circuits and Systems 8(3): 234-244 (1989) |
1 | Keith A. Bowman | [11] |
2 | Chih-Wei Jim Chang | [4] |
3 | Michael Chang | [9] |
4 | Hongyu Chen | [7] [10] [12] [15] |
5 | Chung-Kuan Cheng | [4] [7] [9] [10] [12] [15] |
6 | Nan-Chi Chou | [5] [6] [7] [8] [9] [10] [12] [13] [14] [15] |
7 | Truman Collins | [12] [15] |
8 | Ajay J. Daga | [3] |
9 | Vivek De | [11] |
10 | Yuzheng Ding | [8] [13] |
11 | Hong-Gee Fang | [2] |
12 | Pei-Ning Guo | [6] |
13 | Michael Hutton (Michael D. Hutton, Mike Hutton) | [12] [15] |
14 | Andrew B. Kahng | [7] |
15 | Lalgudi N. Kannan | [2] |
16 | Gershon Kedem | [1] |
17 | Taeho Kgil | [11] |
18 | Jianhua Liu | [9] |
19 | Lung-Tien Liu | [8] [10] |
20 | John F. MacDonald | [7] [9] |
21 | Malgorzata Marek-Sadowska | [4] |
22 | Trevor N. Mudge | [11] |
23 | Sridhar Srinivasan | [12] [15] |
24 | Dongsheng Wang | [5] [6] [14] |
25 | Bo Yao | [7] [10] [12] [15] |
26 | Shuo Zhou | [12] [15] |
27 | Yi Zhu | [12] [15] |
28 | Zhengyong Zhu | [7] |