| 2008 |
|---|
| 13 | EE | Partha Biswas,
Girish Venkataramani:
Comprehensive isomorphic subtree enumeration.
CASES 2008: 177-186 |
| 2007 |
|---|
| 12 | EE | Partha Biswas,
Sudarshan Banerjee,
Nikil Dutt,
Laura Pozzi,
Paolo Ienne:
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
CoRR abs/0710.4820: (2007) |
| 11 | EE | Partha Biswas,
Nikil D. Dutt,
Laura Pozzi,
Paolo Ienne:
Introduction of Architecturally Visible Storage in Instruction Set Extensions.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 435-446 (2007) |
| 2006 |
|---|
| 10 | EE | Partha Biswas,
Nikil D. Dutt,
Paolo Ienne,
Laura Pozzi:
Automatic identification of application-specific functional units with architecturally visible storage.
DATE 2006: 212-217 |
| 9 | EE | Partha Biswas,
Sudarshan Banerjee,
Nikil D. Dutt,
Paolo Ienne,
Laura Pozzi:
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core.
VLSI Design 2006: 651-656 |
| 8 | EE | Aviral Shrivastava,
Partha Biswas,
Ashok Halambi,
Nikil D. Dutt,
Alexandru Nicolau:
Compilation framework for code size reduction using reduced bit-width ISAs (rISAs).
ACM Trans. Design Autom. Electr. Syst. 11(1): 123-146 (2006) |
| 7 | EE | Partha Biswas,
Sudarshan Banerjee,
Nikil D. Dutt,
Laura Pozzi,
Paolo Ienne:
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors.
IEEE Trans. VLSI Syst. 14(7): 754-762 (2006) |
| 2005 |
|---|
| 6 | EE | Partha Biswas,
Sudarshan Banerjee,
Nikil D. Dutt,
Laura Pozzi,
Paolo Ienne:
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement.
DATE 2005: 1246-1251 |
| 5 | EE | Partha Biswas,
Nikil D. Dutt:
Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions.
IEEE Trans. Computers 54(10): 1216-1226 (2005) |
| 2004 |
|---|
| 4 | EE | Partha Biswas,
Vinay Choudhary,
Kubilay Atasu,
Laura Pozzi,
Paolo Ienne,
Nikil Dutt:
Introduction of local memory elements in instruction set extensions.
DAC 2004: 729-734 |
| 2003 |
|---|
| 3 | EE | Partha Biswas,
Nikil D. Dutt:
Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions.
CASES 2003: 104-112 |
| 2002 |
|---|
| 2 | EE | Ashok Halambi,
Aviral Shrivastava,
Partha Biswas,
Nikil D. Dutt,
Alexandru Nicolau:
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs.
DATE 2002: 402-408 |
| 1 | EE | Alexandru Nicolau,
Nikil D. Dutt,
Aviral Shrivastava,
Partha Biswas,
Ashok Halambi:
A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design .
ISSS 2002: 120-125 |
