| 2009 |
|---|
| 46 | EE | Muhammad Umar Farooq,
Lizy Kurian John,
Margarida F. Jacome:
Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures.
HiPEAC 2009: 324-338 |
| 2007 |
|---|
| 45 | EE | Fadi A. Zaraket,
John Pape,
Adnan Aziz,
Margarida F. Jacome,
Sarfraz Khurshid:
Global Optimization of Compositional Systems.
FMCAD 2007: 93-100 |
| 44 | EE | Ayis Ziotopoulos,
Margarida F. Jacome,
Gustavo de Veciana:
An RFID-Based Platform Supporting Context-Aware Computing in Complex Spaces.
MDM 2007: 294-298 |
| 43 | EE | Elias Mizan,
Tileli Amimeur,
Margarida F. Jacome:
Self-Imposed Temporal Redundancy: An Efficient Technique to Enhance the Reliability of Pipelined Functional Units.
SBAC-PAD 2007: 45-53 |
| 42 | EE | Chen He,
Margarida F. Jacome:
Defect-Aware High-Level Synthesis Targeted at Reconfigurable Nanofabrics.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 817-833 (2007) |
| 2006 |
|---|
| 41 | EE | Chen He,
Margarida F. Jacome:
RAS-NANO: a reliability-aware synthesis framework for reconfigurable nanofabrics.
DATE 2006: 1179-1184 |
| 2005 |
|---|
| 40 | EE | Andrey V. Zykov,
Elias Mizan,
Margarida F. Jacome,
Gustavo de Veciana,
Ajay Subramanian:
High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offs.
DAC 2005: 270-273 |
| 39 | | Margarida F. Jacome,
Anand Ramachandran:
Power Aware Embedded Computing.
The Industrial Information Technology Handbook 2005: 1-23 |
| 38 | EE | Chen He,
Margarida F. Jacome,
Gustavo de Veciana:
A Reconfiguration-Based Defect-Tolerant Design Paradigm for Nanotechnologies.
IEEE Design & Test of Computers 22(4): 316-326 (2005) |
| 37 | EE | Satish Pillai,
Margarida F. Jacome:
Predicated switching - optimizing speculation on EPIC machines.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 318-335 (2005) |
| 36 | EE | Anand Ramachandran,
Margarida F. Jacome:
Xtream-fit: an energy-delay efficient data memory subsystem for embedded media processing.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 832-848 (2005) |
| 2004 |
|---|
| 35 | EE | Margarida F. Jacome,
Chen He,
Gustavo de Veciana,
Stephen Bijansky:
Defect tolerant probabilistic design paradigm for nanotechnologies.
DAC 2004: 596-601 |
| 2003 |
|---|
| 34 | EE | Anand Ramachandran,
Margarida F. Jacome:
Xtream-Fit: an energy-delay efficient data memory subsystem for embedded media processing.
DAC 2003: 137-142 |
| 33 | EE | Jeffry T. Russell,
Margarida F. Jacome:
Architecture-level performance evaluation of component-based embedded systems.
DAC 2003: 396-401 |
| 32 | EE | Satish Pillai,
Margarida F. Jacome:
Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling.
DATE 2003: 10422-10427 |
| 31 | EE | Jeffry T. Russell,
Margarida F. Jacome:
Embedded Architect: A Tool for Early Performance Evaluation of Embedded Software.
ICSE 2003: 824-825 |
| 30 | EE | Chen He,
Marcello Lajolo,
Margarida F. Jacome:
A Case Study of a System Level Approach to Exploration of Queuing Management Schemes for Input Queue Packet Switches.
PDP 2003: 401-408 |
| 29 | EE | Margarida F. Jacome,
Francky Catthoor:
Special issue on power-aware embedded computing.
ACM Trans. Embedded Comput. Syst. 2(3): 251-254 (2003) |
| 2002 |
|---|
| 28 | EE | Jeffry T. Russell,
Margarida F. Jacome:
Scenario-based software characterization as a contingency to traditional program profiling.
CASES 2002: 170-177 |
| 27 | EE | Viktor S. Lapinskii,
Margarida F. Jacome,
Gustavo de Veciana:
Cluster assignment for high-performance embedded VLIW processors.
ACM Trans. Design Autom. Electr. Syst. 7(3): 430-454 (2002) |
| 26 | EE | Cagdas Akturan,
Margarida F. Jacome:
RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1395-1415 (2002) |
| 25 | EE | Viktor S. Lapinskii,
Margarida F. Jacome,
Gustavo de Veciana:
Application-specific clustered VLIW datapaths: early exploration on a parameterized design space.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(8): 889-903 (2002) |
| 2001 |
|---|
| 24 | EE | Cagdas Akturan,
Margarida F. Jacome:
RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors.
CODES 2001: 67-72 |
| 23 | EE | Margarida F. Jacome,
Gustavo de Veciana,
Satish Pillai:
Clustered VLIW Architectures with Predicated Switching.
DAC 2001: 696-701 |
| 22 | EE | Viktor S. Lapinskii,
Margarida F. Jacome,
Gustavo de Veciana:
High-Quality Operation Binding for Clustered VLIW Datapaths.
DAC 2001: 702-707 |
| 21 | EE | Cagdas Akturan,
Margarida F. Jacome:
CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors.
ICCAD 2001: 112-118 |
| 20 | EE | Margarida F. Jacome,
Helvio P. Peixoto:
A Survey of Digital Design Reuse.
IEEE Design & Test of Computers 18(3): 98-107 (2001) |
| 2000 |
|---|
| 19 | EE | Helvio P. Peixoto,
Margarida F. Jacome:
A new technique for estimating lower bounds on latency for high level synthesis.
ACM Great Lakes Symposium on VLSI 2000: 129-132 |
| 18 | EE | R. Anand,
Margarida F. Jacome,
Gustavo de Veciana:
Heuristic tradeoffs between latency and energy consumption in register assignment.
CODES 2000: 115-119 |
| 17 | | Margarida F. Jacome,
Gustavo de Veciana,
Viktor S. Lapinskii:
Exploring Performance Tradeoffs for Clustered VLIW ASIPs.
ICCAD 2000: 504-510 |
| 16 | EE | Satish Pillai,
Margarida F. Jacome:
Symbolic Binding for Clustered VLIW ASIPs.
ICCD 2000: 437-444 |
| 15 | EE | Cagdas Akturan,
Margarida F. Jacome:
FDRA: A Software-Pipelining Algorithm for Embedded VLIW Processors.
ISSS 2000: 34-40 |
| 14 | | Hugo A. Andrade,
Margarida F. Jacome:
The Common Hardware and Software Object Model: CHSOM.
PDPTA 2000 |
| 13 | EE | Helvio P. Peixoto,
Margarida F. Jacome,
Ander Royo:
A Tight Area Upper Bound for Slicing Floorplans.
VLSI Design 2000: 280- |
| 12 | EE | Margarida F. Jacome,
Gustavo de Veciana:
Design Challenges for New Application-Specific Processors.
IEEE Design & Test of Computers 17(2): 40-50 (2000) |
| 1999 |
|---|
| 11 | EE | Margarida F. Jacome,
Gustavo de Veciana,
Cagdas Akturan:
Resource constrained dataflow retiming heuristics for VLIW ASIPs.
CODES 1999: 12-16 |
| 10 | EE | Margarida F. Jacome,
Helvio P. Peixoto,
Ander Royo,
Juan Carlos López:
The Design Space Layer: Supporting Early Design Space Exploration for Core-Based Designs.
DATE 1999: 676-683 |
| 9 | EE | Margarida F. Jacome,
Gustavo de Veciana:
Lower bound on latency for VLIW ASIP datapaths.
ICCAD 1999: 261-269 |
| 1998 |
|---|
| 8 | EE | Gustavo de Veciana,
Margarida F. Jacome,
J.-H. Guo:
Hierarchical Algorithms for Assessing Probabilistic Constraints on System Performance.
DAC 1998: 251-256 |
| 7 | EE | Pedro Merino,
Margarida F. Jacome,
Juan Carlos López:
A Methodology for Task Based Partitioning and Scheduling of Dynamically Reconfigurable Systems.
FCCM 1998: 324-325 |
| 6 | EE | Pedro Merino,
Juan Carlos López,
Margarida F. Jacome:
A Hardwar Operating System for Dynamic Reconfiguration of FPGAs.
FPL 1998: 431-435 |
| 1997 |
|---|
| 5 | EE | Helvio P. Peixoto,
Margarida F. Jacome:
Algorithm and architecture-level design space exploration using hierarchical data flows.
ASAP 1997: 272-282 |
| 4 | EE | Margarida F. Jacome,
Viktor S. Lapinskii:
NREC: Risk Assessment and Planning of Complex Designs.
IEEE Design & Test of Computers 14(1): 42-49 (1997) |
| 1996 |
|---|
| 3 | EE | Margarida F. Jacome,
Stephen W. Director:
A formal basis for design process planning and management.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1197-1210 (1996) |
| 1994 |
|---|
| 2 | EE | Margarida F. Jacome,
Stephen W. Director:
A formal basis for design process planning and management.
ICCAD 1994: 516-521 |
| 1992 |
|---|
| 1 | EE | Margarida F. Jacome,
Stephen W. Director:
Design Process Management for CAD Frameworks.
DAC 1992: 500-505 |
