2008 |
30 | EE | Jose Antonio Perez-Carrasco,
Carmen Serrano,
Begoña Acha,
Teresa Serrano-Gotarredona,
Bernabé Linares-Barranco:
Event based vision sensing and processing.
ICIP 2008: 1392-1395 |
29 | EE | Juan Antonio Leñero-Bardallo,
Teresa Serrano-Gotarredona,
Bernabé Linares-Barranco:
Compact calibration circuit for large neuromorphic arrays.
ISCAS 2008: 1776-1779 |
28 | EE | Jose Antonio Perez-Carrasco,
Teresa Serrano-Gotarredona,
Carmen Serrano-Gotarredona,
Begoña Acha,
Bernabé Linares-Barranco:
High-speed character recognition system based on a complex hierarchical AER architecture.
ISCAS 2008: 2150-2153 |
27 | EE | Carlos Zamarreno-Ramos,
Rafael Serrano-Gotarredona,
Teresa Serrano-Gotarredona,
Bernabé Linares-Barranco:
LVDS interface for AER links with burst mode operation capability.
ISCAS 2008: 644-647 |
26 | EE | Luis Camunas-Mesa,
Antonio Acosta-Jimenez,
Teresa Serrano-Gotarredona,
Bernabé Linares-Barranco:
Fully digital AER convolution chip for vision processing.
ISCAS 2008: 652-655 |
2007 |
25 | EE | Bernabé Linares-Barranco,
Teresa Serrano-Gotarredona:
A Physical Interpretation of the Distance Term in Pelgrom's Mismatch Model results in very Efficient CAD.
ISCAS 2007: 1561-1564 |
24 | EE | Jesús Costas-Santos,
Teresa Serrano-Gotarredona,
Rafael Serrano-Gotarredona,
Bernabé Linares-Barranco:
An AER Contrast Retina with On-Chip Calibration.
ISCAS 2007: 3075-3078 |
23 | EE | Rafael Serrano-Gotarredona,
Teresa Serrano-Gotarredona,
Antonio Acosta-Jimenez,
Alejandro Linares-Barranco,
Gabriel Jiménez-Moreno,
Antón Civit Balcells,
Bernabé Linares-Barranco:
Spike Events Processing for Vision Systems.
ISCAS 2007: 841-844 |
22 | EE | Bernabé Linares-Barranco,
Teresa Serrano-Gotarredona:
On an Efficient CAD Implementation of the Distance Term in Pelgrom's Mismatch Model.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1534-1538 (2007) |
2006 |
21 | EE | Rafael Serrano-Gotarredona,
Teresa Serrano-Gotarredona,
Antonio Acosta-Jimenez,
Bernabé Linares-Barranco:
An arbitrary kernel convolution AER-transceiver chip for real-time image filtering.
ISCAS 2006 |
20 | EE | Rafael Serrano-Gotarredona,
Bernabé Linares-Barranco,
Teresa Serrano-Gotarredona,
Antonio Acosta-Jimenez,
Alejandro Linares-Barranco,
Rafael Paz-Vicente,
Francisco Gomez-Rodriguez:
High-speed image processing with AER-based components.
ISCAS 2006 |
19 | EE | Teresa Serrano-Gotarredona,
Bernabé Linares-Barranco:
A Low-Power Current Mode Fuzzy-ART Cell.
IEEE Transactions on Neural Networks 17(6): 1666-1673 (2006) |
2005 |
18 | EE | Rafael Serrano-Gotarredona,
Matthias Oster,
Patrick Lichtsteiner,
Alejandro Linares-Barranco,
Rafael Paz-Vicente,
Francisco Gomez-Rodriguez,
Håvard Kolle Riis,
Tobi Delbrück,
Shih-Chii Liu,
S. Zahnd,
Adrian M. Whatley,
Rodney J. Douglas,
Philipp Häfliger,
Gabriel Jiménez-Moreno,
Antón Civit,
Teresa Serrano-Gotarredona,
Antonio Acosta-Jimenez,
Bernabé Linares-Barranco:
AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems.
NIPS 2005 |
2004 |
17 | | Teresa Serrano-Gotarredona,
Rafael Serrano-Gotarredona,
Bernabé Linares-Barranco:
Hardware implementation of complex reaction-diffusion neural networks using log-domain techniques.
ISCAS (1) 2004: 301-304 |
16 | | Bernabé Linares-Barranco,
Teresa Serrano-Gotarredona,
Rafael Serrano-Gotarredona,
Luis A. Camuñas:
On leakage current temperature characterization using sub-pico-ampere circuit techniques.
ISCAS (1) 2004: 361-364 |
15 | | Bernabé Linares-Barranco,
Teresa Serrano-Gotarredona,
Rafael Serrano-Gotarredona,
Gustavo Vicente-Sánchez:
On mismatch properties of MOS and resistors calibrated ladder structures.
ISCAS (1) 2004: 377-380 |
14 | EE | Teresa Serrano-Gotarredona,
Bernabé Linares-Barranco,
Jesús Velarde-Ramírez:
A precise CMOS mismatch model for analog design from weak to strong inversion.
ISCAS (1) 2004: 753-756 |
13 | | Bernabé Linares-Barranco,
Teresa Serrano-Gotarredona,
J. Ramos-Martos,
J. Ceballos-Cáaceres,
J. M. Mora,
Alejandro Linares-Barranco:
A precise 90/spl deg/ quadrature OTA-C VCO between 50-130 MHz.
ISCAS (4) 2004: 541-544 |
12 | | Bernabé Linares-Barranco,
Teresa Serrano-Gotarredona,
Rafael Serrano-Gotarredona,
Jesús Costas-Santos:
A new charge-packet driven mismatch-calibrated integrate-and-fire neuron for processing positive and negative signals in AER based systems.
ISCAS (5) 2004: 744-747 |
2000 |
11 | EE | Teresa Serrano-Gotarredona,
Bernabé Linares-Barranco,
Andreas G. Andreou:
Programmable Kernel Analog VLSI Convolution Chip for Real Time Vision Processing.
IJCNN (4) 2000: 62-65 |
10 | EE | Teresa Serrano-Gotarredona,
Andreas G. Andreou,
Bernabé Linares-Barranco:
A Programmable VLSI Filter Architecture for Application in Real-Time Vision Processing Systems.
Int. J. Neural Syst. 10(3): 179-190 (2000) |
1999 |
9 | EE | Teresa Serrano-Gotarredona,
Bernabé Linares-Barranco,
Andreas G. Andreou:
A general subthreshold MOS translinear theorem.
ISCAS (2) 1999: 302-305 |
8 | EE | Teresa Serrano-Gotarredona,
Andreas G. Andreou,
Bernabé Linares-Barranco:
Programmable 2D image filter for AER vision processing.
ISCAS (4) 1999: 159-162 |
7 | | Teresa Serrano-Gotarredona,
Bernabé Linares-Barranco:
Adaptive Resonance Theory Microchips.
IWANN (1) 1999: 737-746 |
6 | EE | Teresa Serrano-Gotarredona,
Ángel Rodríguez-Vázquez:
On the Design of Second Order Dynamics Reaction-Diffusion CNNs.
VLSI Signal Processing 23(2-3): 351-372 (1999) |
1996 |
5 | EE | Teresa Serrano-Gotarredona,
Bernabé Linares-Barranco:
A real-time clustering microchip neural engine.
IEEE Trans. VLSI Syst. 4(2): 195-209 (1996) |
4 | EE | Teresa Serrano-Gotarredona,
Bernabé Linares-Barranco:
A Modified ART 1 Algorithm more Suitable for VLSI Implementations.
Neural Networks 9(6): 1025-1043 (1996) |
1995 |
3 | | Teresa Serrano-Gotarredona,
Bernabé Linares-Barranco:
Experimental Results of an Analog Current-Mode ART1 Chip.
ISCAS 1995: 1672-1675 |
1994 |
2 | | Teresa Serrano-Gotarredona,
Bernabé Linares-Barranco:
A Modular Current-Mode High-Precision Winner-Take-All Circuit.
ISCAS 1994: 557-560 |
1 | EE | Teresa Serrano-Gotarredona,
Bernabé Linares-Barranco,
José Luis Huertas:
A Real Time Clustering CMOS Neural Engine.
NIPS 1994: 755-762 |