Nan-Chi Chou

2007
16	EE	Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng: Efficient Timing Analysis With Known False Paths Using Biclique Covering. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 959-969 (2007)
2005
15	EE	Peter Suaris, Dongsheng Wang, Nan-Chi Chou: A practical cut-based physical retiming algorithm for field programmable gate arrays. ASP-DAC 2005: 1027-1030
14	EE	Yuzheng Ding, Peter Suaris, Nan-Chi Chou: The effect of post-layout pin permutation on timing. FPGA 2005: 41-50
13		Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris: Improving the efficiency of static timing analysis with false paths. ICCAD 2005: 527-531
12	EE	Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris: Unified quadratic programming approach for mixed mode placement. ISPD 2005: 193-199
2004
11	EE	Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris: Fast adders in modern FPGAs. FPGA 2004: 250
10	EE	Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou: Incremental physical resynthesis for timing optimization. FPGA 2004: 99-108
2003
9	EE	Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu: An algebraic multigrid solver for analytical placement with layout based clustering. DAC 2003: 794-799
8	EE	Peter Suaris, Dongsheng Wang, Pei-Ning Guo, Nan-Chi Chou: A physical retiming algorithm for field programmable gate arrays. FPGA 2003: 247
7	EE	Dongsheng Wang, Peter Suaris, Nan-Chi Chou: A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages. PATMOS 2003: 511-519
1995
6	EE	Nan-Chi Chou, Chung-Kuan Cheng: On general zero-skew clock net construction. IEEE Trans. VLSI Syst. 3(1): 141-146 (1995)
5	EE	Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof: Local ratio cut and set covering partitioning for huge logic emulation systems. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1085-1092 (1995)
1994
4	EE	Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof: Circuit Partitioning for Huge Logic Emulation Systems. DAC 1994: 244-249
3	EE	So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu: A multi-probe approach for MCM substrate testing. IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 110-121 (1994)
1993
2	EE	Lung-Tien Liu, Minshine Shih, Nan-Chi Chou, Chung-Kuan Cheng, Walter H. Ku: Performance-driven partitioning using retiming and replication. ICCAD 1993: 296-299
1992
1	EE	So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu: An optimal probe testing algorthm for the connectivity verification of MCM substrates. ICCAD 1992: 264-267

Coauthor Index

1	Michael Chang	[11]
2	Hongyu Chen	[9] [12] [13] [16]
3	Chung-Kuan Cheng	[1] [2] [3] [4] [5] [6] [9] [11] [12] [13] [16]
4	Truman Collins	[13] [16]
5	Wei-Jin Dai	[4] [5]
6	Yuzheng Ding	[10] [14]
7	Pei-Ning Guo	[8]
8	T. C. Hu	[1] [3]
9	Michael Hutton (Michael D. Hutton, Mike Hutton)	[13] [16]
10	Andrew B. Kahng	[9]
11	Walter H. Ku	[2]
12	Rodney Lindelof	[4] [5]
13	Jianhua Liu	[11]
14	Lung-Tien Liu	[2] [4] [5] [10] [12]
15	John F. MacDonald	[9] [11]
16	Minshine Shih	[2]
17	Sridhar Srinivasan	[13] [16]
18	Peter Suaris (Peter Ramyalal Suaris)	[7] [8] [9] [10] [11] [12] [13] [14] [15] [16]
19	Dongsheng Wang	[7] [8] [15]
20	Bo Yao	[9] [12] [13] [16]
21	So-Zen Yao	[1] [3]
22	Shuo Zhou	[13] [16]
23	Yi Zhu	[13] [16]
24	Zhengyong Zhu	[9]