| 2008 |
|---|
| 120 | EE | Chin-Lung Su,
Chih-Wea Tsai,
Cheng-Wen Wu,
Chien-Chung Hung,
Young-Shying Chen,
Ding-Yeong Wang,
Yuan-Jen Lee,
Ming-Jer Kao:
Write Disturbance Modeling and Testing for MRAM.
IEEE Trans. VLSI Syst. 16(3): 277-288 (2008) |
| 2007 |
|---|
| 119 | EE | Yu-Tsao Hsing,
Chun-Chieh Huang,
Jen-Chieh Yeh,
Cheng-Wen Wu:
SDRAM Delay Fault Modeling and Performance Testing.
VTS 2007: 53-58 |
| 118 | EE | Cheng-Wen Wu:
SOC Testing Methodology and Practice
CoRR abs/0710.4669: (2007) |
| 117 | EE | Rei-Fu Huang,
Chao-Hsun Chen,
Cheng-Wen Wu:
Economic Aspects of Memory Built-in Self-Repair.
IEEE Design & Test of Computers 24(2): 164-172 (2007) |
| 116 | EE | Rei-Fu Huang,
Jin-Fu Li,
Jen-Chieh Yeh,
Cheng-Wen Wu:
Raisin: Redundancy Analysis Algorithm Simulation.
IEEE Design & Test of Computers 24(4): 386-396 (2007) |
| 115 | EE | Chih-Yen Lo,
Chen-Hsing Wang,
Kuo-Liang Cheng,
Jing-Reng Huang,
Chih-Wea Wang,
Shin-Moe Wang,
Cheng-Wen Wu:
STEAC: A Platform for Automatic SOC Test Integration.
IEEE Trans. VLSI Syst. 15(5): 541-545 (2007) |
| 114 | EE | Jen-Chieh Yeh,
Kuo-Liang Cheng,
Yung-Fa Chou,
Cheng-Wen Wu:
Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1101-1113 (2007) |
| 2006 |
|---|
| 113 | EE | Chen-Hsing Wang,
Chih-Yen Lo,
Min-Sheng Lee,
Jen-Chieh Yeh,
Chih-Tsun Huang,
Cheng-Wen Wu,
Shi-Yu Huang:
A network security processor design based on an integrated SOC design and test platform.
DAC 2006: 490-495 |
| 112 | EE | Mu-Hsien Hsu,
Yu-Tsao Hsing,
Jen-Chieh Yeh,
Cheng-Wen Wu:
Fault-Pattern Oriented Defect Diagnosis for Flash Memory.
MTDT 2006: 3-8 |
| 111 | EE | Yu-Ying Hsiao,
Chao-Hsun Chen,
Cheng-Wen Wu:
A Built-In Self-Repair Scheme for NOR-Type Flash Memory.
VTS 2006: 114-119 |
| 110 | EE | Cheng-Wen Wu:
Session Abstract.
VTS 2006: 128-129 |
| 109 | EE | Shyue-Kung Lu,
Yu-Chen Tsai,
Chih-Hsien Hsu,
Kuo-Hua Wang,
Cheng-Wen Wu:
Efficient built-in redundancy analysis for embedded memories with 2-D redundancy.
IEEE Trans. VLSI Syst. 14(1): 34-42 (2006) |
| 2005 |
|---|
| 108 | EE | Chih-Pin Su,
Chia-Lung Horng,
Chih-Tsun Huang,
Cheng-Wen Wu:
A configurable AES processor for enhanced security.
ASP-DAC 2005: 361-366 |
| 107 | EE | Chih-Pin Su,
Chen-Hsing Wang,
Kuo-Liang Cheng,
Chih-Tsun Huang,
Cheng-Wen Wu:
Design and test of a scalable security processor.
ASP-DAC 2005: 372-375 |
| 106 | EE | Yu-Chun Dawn,
Jen-Chieh Yeh,
Cheng-Wen Wu,
Chia-Ching Wang,
Yung-Chen Lin,
Chao-Hsun Chen:
Flash Memory Die Sort by a Sample Classification Method.
Asian Test Symposium 2005: 182-187 |
| 105 | EE | Cheng-Wen Wu:
SOC Testing Methodology and Practice.
DATE 2005: 1120-1121 |
| 104 | EE | Chin-Lung Su,
Yi-Ting Yeh,
Cheng-Wen Wu:
An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement.
DFT 2005: 81-92 |
| 103 | EE | Jen-Chieh Yeh,
Yan-Ting Lai,
Yuan-Yuan Shih,
Cheng-Wen Wu,
Chien-Hung Ho,
Yen-Tai Lin:
Flash Memory Built-In Self-Diagnosis with Test Mode Control.
VTS 2005: 15-20 |
| 102 | EE | Chun-Chieh Wang,
Jing-Jia Liou,
Yen-Lin Peng,
Chih-Tsun Huang,
Cheng-Wen Wu:
A BIST Scheme for FPGA Interconnect Delay Faults.
VTS 2005: 201-206 |
| 101 | EE | Jin-Fu Li,
Jen-Chieh Yeh,
Rei-Fu Huang,
Cheng-Wen Wu:
A built-in self-repair design for RAMs with 2-D redundancy.
IEEE Trans. VLSI Syst. 13(6): 742-745 (2005) |
| 2004 |
|---|
| 100 | EE | Rei-Fu Huang,
Yan-Ting Lai,
Yung-Fa Chou,
Cheng-Wen Wu:
SRAM delay fault modeling and test algorithm development.
ASP-DAC 2004: 104-109 |
| 99 | EE | Mao-Yin Wang,
Chih-Pin Su,
Chih-Tsun Huang,
Cheng-Wen Wu:
An HMAC processor with integrated SHA-1 and MD5 algorithms.
ASP-DAC 2004: 456-458 |
| 98 | EE | Chih-Tsun Huang,
Jen-Chieh Yeh,
Yuan-Yuan Shih,
Rei-Fu Huang,
Cheng-Wen Wu:
On Test and Diagnostics of Flash Memories.
Asian Test Symposium 2004: 260-265 |
| 97 | EE | Rei-Fu Huang,
Chin-Lung Su,
Cheng-Wen Wu,
Shen-Tien Lin,
Kun-Lun Luo,
Yeong-Jar Chang:
Fail Pattern Identification for Memory Built-In Self-Repair.
Asian Test Symposium 2004: 366-371 |
| 96 | EE | Hao-Chiao Hong,
Cheng-Wen Wu,
Kwang-Ting Cheng:
A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose.
Asian Test Symposium 2004: 62-67 |
| 95 | EE | Yu-Tsao Hsing,
Chih-Wea Wang,
Ching-Wei Wu,
Chih-Tsun Huang,
Cheng-Wen Wu:
Failure Factor Based Yield Enhancement for SRAM Designs.
DFT 2004: 20-28 |
| 94 | EE | Yen-Lin Peng,
Jing-Jia Liou,
Chih-Tsun Huang,
Cheng-Wen Wu:
An Application-Independent Delay Testing Methodology for Island-Style FPGA.
DFT 2004: 478-486 |
| 93 | EE | Chin-Lung Su,
Rei-Fu Huang,
Cheng-Wen Wu,
Chien-Chung Hung,
Ming-Jer Kao,
Yeong-Jar Chang,
Wen Ching Wu:
MRAM Defect Analysis and Fault Modeli.
ITC 2004: 124-133 |
| 92 | EE | Li-Ming Denq,
Rei-Fu Huang,
Cheng-Wen Wu,
Yeong-Jar Chang,
Wen Ching Wu:
A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.
MTDT 2004: 65-69 |
| 91 | EE | Bin-Hong Lin,
Cheng-Wen Wu,
Hwei-Tsu Ann Luh:
Efficient and Economical Test Equipment Setup Using Procorrelation.
IEEE Design & Test of Computers 21(1): 34-43 (2004) |
| 90 | EE | Chih-Pin Su,
Cheng-Wen Wu:
A Graph-Based Approach to Power-Constrained SOC Test Scheduling.
J. Electronic Testing 20(1): 45-60 (2004) |
| 2003 |
|---|
| 89 | EE | Rei-Fu Huang,
Yung-Fa Chou,
Cheng-Wen Wu:
Defect Oriented Fault Analysis for SRAM.
Asian Test Symposium 2003: 256-261 |
| 88 | EE | Chin-Lung Su,
Rei-Fu Huang,
Cheng-Wen Wu:
A Processor-Based Built-In Self-Repair Design for Embedded Memories.
Asian Test Symposium 2003: 366-371 |
| 87 | EE | Kuo-Liang Cheng,
Chih-Wea Wang,
Jih-Nung Lee,
Yung-Fa Chou,
Chih-Tsun Huang,
Cheng-Wen Wu:
FAME: A Fault-Pattern Based Memory Failure Analysis Framework.
ICCAD 2003: 595-598 |
| 86 | EE | Shyue-Kung Lu,
Jian-Long Chen,
Cheng-Wen Wu,
Ken-Feng Chang,
Shi-Yu Huang:
Combinational circuit fault diagnosis using logic emulation.
ISCAS (5) 2003: 549-552 |
| 85 | EE | Chih-Wea Wang,
Kuo-Liang Cheng,
Jih-Nung Lee,
Yung-Fa Chou,
Chih-Tsun Huang,
Cheng-Wen Wu,
Frank Huang,
Hong-Tzer Yang:
Fault Pattern Oriented Defect Diagnosis for Memories.
ITC 2003: 29-38 |
| 84 | EE | Jin-Fu Li,
Jen-Chieh Yeh,
Rei-Fu Huang,
Cheng-Wen Wu,
Peir-Yuan Tsai,
Archer Hsu,
Eugene Chow:
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy.
ITC 2003: 393-402 |
| 83 | EE | Rei-Fu Huang,
Li-Ming Denq,
Cheng-Wen Wu,
Jin-Fu Li:
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories.
MTDT 2003: 53- |
| 82 | EE | Chih-Wea Wang,
Kuo-Liang Cheng,
Chih-Tsun Huang,
Cheng-Wen Wu:
Test and Diagnosis of Word-Oriented Multiport Memories.
VTS 2003: 248-253 |
| 81 | EE | Jin-Hua Hong,
Cheng-Wen Wu:
Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm.
IEEE Trans. VLSI Syst. 11(3): 474-484 (2003) |
| 80 | EE | Chih-Tsun Huang,
Chi-Feng Wu,
Jin-Fu Li,
Cheng-Wen Wu:
Built-in redundancy analysis for memory yield improvement.
IEEE Transactions on Reliability 52(4): 386-399 (2003) |
| 79 | EE | Jin-Fu Li,
Ruey-Shing Tzeng,
Cheng-Wen Wu:
Testing and Diagnosis Methodologies for Embedded Content Addressable Memories.
J. Electronic Testing 19(2): 207-215 (2003) |
| 78 | EE | Hong-Chou Kao,
Ming-Fu Tsai,
Shi-Yu Huang,
Cheng-Wen Wu,
Wen-Feng Chang,
Shyue-Kung Lu:
Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults.
J. Inf. Sci. Eng. 19(4): 571-587 (2003) |
| 77 | EE | Shao-Hui Shieh,
Cheng-Wen Wu:
Asymmetric High-Radix Signed-Digit Number Systems for Carry-Free Addition.
J. Inf. Sci. Eng. 19(6): 1015-1039 (2003) |
| 2002 |
|---|
| 76 | EE | Chih-Wea Wang,
Jing-Reng Huang,
Yen-Fu Lin,
Kuo-Liang Cheng,
Chih-Tsun Huang,
Cheng-Wen Wu,
Youn-Long Lin:
Test Scheduling of BISTed Memory Cores for SOC.
Asian Test Symposium 2002: 356- |
| 75 | EE | Huan-Shan Hsu,
Jing-Reng Huang,
Kuo-Liang Cheng,
Chih-Wea Wang,
Chih-Tsun Huang,
Cheng-Wen Wu,
Youn-Long Lin:
Test Scheduling and Test Access Architecture Optimization for System-on-Chip.
Asian Test Symposium 2002: 411- |
| 74 | EE | Hao-Chiao Hong,
Jiun-Lang Huang,
Kwang-Ting Cheng,
Cheng-Wen Wu:
On-chip Analog Response Extraction with 1-Bit ? - Modulators.
Asian Test Symposium 2002: 49- |
| 73 | EE | Jin-Fu Li,
Hsin-Jung Huang,
Jeng-Bin Chen,
Chih-Pin Su,
Cheng-Wen Wu,
Chuang Cheng,
Shao-I Chen,
Chi-Yi Hwang,
Hsiao-Ping Lin:
A Hierarchical Test Scheme for System-On-Chip Designs.
DATE 2002: 486-490 |
| 72 | EE | Jen-Chieh Yeh,
Chi-Feng Wu,
Kuo-Liang Cheng,
Yung-Fa Chou,
Chih-Tsun Huang,
Cheng-Wen Wu:
Flash Memory Built-In Self-Test Using March-Like Algorithm.
DELTA 2002: 137-141 |
| 71 | EE | Rei-Fu Huang,
Jin-Fu Li,
Jen-Chieh Yeh,
Cheng-Wen Wu:
A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories.
IOLTW 2002: 262- |
| 70 | EE | Sau-Kwo Chiu,
Jen-Chieh Yeh,
Chih-Tsun Huang,
Cheng-Wen Wu:
Diagonal Test and Diagnostic Schemes for Flash Memorie.
ITC 2002: 37-46 |
| 69 | EE | Rei-Fu Huang,
Jin-Fu Li,
Jen-Chieh Yeh,
Cheng-Wen Wu:
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories.
MTDT 2002: 68- |
| 68 | EE | Kuo-Liang Cheng,
Jen-Chieh Yeh,
Chih-Wea Wang,
Chih-Tsun Huang,
Cheng-Wen Wu:
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics.
VTS 2002: 281-288 |
| 67 | EE | Jin-Fu Li,
Ruey-Shing Tzeng,
Cheng-Wen Wu:
Testing and Diagnosing Embedded Content Addressable Memories.
VTS 2002: 389-394 |
| 66 | EE | Jin-Fu Li,
Hsin-Jung Huang,
Jeng-Bin Chen,
Chih-Pin Su,
Cheng-Wen Wu,
Chuang Cheng,
Shao-I Chen,
Chi-Yi Hwang,
Hsiao-Ping Lin:
A Hierarchical Test Methodology for Systems on Chip.
IEEE Micro 22(5): 69-81 (2002) |
| 65 | EE | Jin-Fu Li,
Cheng-Wen Wu:
Efficient FFT network testing and diagnosis schemes.
IEEE Trans. VLSI Syst. 10(3): 267-278 (2002) |
| 64 | EE | Kuo-Liang Cheng,
Ming-Fu Tsai,
Cheng-Wen Wu:
Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1328-1336 (2002) |
| 63 | EE | Chi-Feng Wu,
Chih-Tsun Huang,
Kuo-Liang Cheng,
Cheng-Wen Wu:
Fault simulation and test algorithm generation for random accessmemories.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 480-490 (2002) |
| 62 | EE | Jin-Fu Li,
Ruey-Shing Tzeng,
Cheng-Wen Wu:
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test.
J. Electronic Testing 18(4-5): 515-527 (2002) |
| 61 | EE | Chih-Wea Wang,
Chi-Feng Wu,
Jin-Fu Li,
Cheng-Wen Wu,
Tony Teng,
Kevin Chiu,
Hsiao-Ping Lin:
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM.
J. Electronic Testing 18(6): 637-647 (2002) |
| 2001 |
|---|
| 60 | EE | Ching-Hong Tsai,
Cheng-Wen Wu:
Processor-programmable memory BIST for bus-connected embedded memories.
ASP-DAC 2001: 325-330 |
| 59 | EE | Chung-Hsien Wu,
Jin-Hua Hong,
Cheng-Wen Wu:
RSA cryptosystem design based on the Chinese remainder theorem.
ASP-DAC 2001: 391-395 |
| 58 | EE | Chih-Wea Wang,
Ruey-Shing Tzeng,
Chi-Feng Wu,
Chih-Tsun Huang,
Cheng-Wen Wu,
Shi-Yu Huang,
Shyh-Horng Lin,
Hsin-Po Wang:
A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters.
Asian Test Symposium 2001: 103- |
| 57 | EE | Kuo-Liang Cheng,
Chia-Ming Hsueh,
Jing-Reng Huang,
Jen-Chieh Yeh,
Chih-Tsun Huang,
Cheng-Wen Wu:
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip.
Asian Test Symposium 2001: 91-96 |
| 56 | EE | Chi-Feng Wu,
Chih-Tsun Huang,
Kuo-Liang Cheng,
Chih-Wea Wang,
Cheng-Wen Wu:
Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories.
DAC 2001: 301-306 |
| 55 | EE | Jin-Fu Li,
Cheng-Wen Wu:
Memory fault diagnosis by syndrome compression.
DATE 2001: 97-101 |
| 54 | | Jin-Fu Li,
Kuo-Liang Cheng,
Chih-Tsun Huang,
Cheng-Wen Wu:
March-based RAM diagnosis algorithms for stuck-at and coupling faults.
ITC 2001: 758-767 |
| 53 | EE | Kuo-Liang Cheng,
Ming-Fu Tsai,
Cheng-Wen Wu:
Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories.
VTS 2001: 225-230 |
| 52 | EE | Shih-Arn Hwang,
Cheng-Wen Wu:
Unified VLSI systolic array design for LZ data compression.
IEEE Trans. VLSI Syst. 9(4): 489-499 (2001) |
| 51 | EE | Chung-Hsien Wu,
Jin-Hua Hong,
Cheng-Wen Wu:
VLSI Design of RSA Cryptosystem Based on the Chinese Remainder Theorem.
J. Inf. Sci. Eng. 17(6): 967-980 (2001) |
| 2000 |
|---|
| 50 | EE | Chih-Tsun Huang,
Jing-Reng Huang,
Cheng-Wen Wu:
A programmable built-in self-test core for embedded memories.
ASP-DAC 2000: 11-12 |
| 49 | EE | Jin-Hua Hong,
Cheng-Wen Wu:
Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem.
ASP-DAC 2000: 565-570 |
| 48 | EE | Lijian Li,
Xiaoyang Yu,
Cheng-Wen Wu,
Yinghua Min:
A waveform simulator based on Boolean process.
Asian Test Symposium 2000: 145-150 |
| 47 | EE | Shyue-Kung Lu,
Jeh-Sheng Shih,
Cheng-Wen Wu:
A Testable/Fault Tolerant FFT Processor Design.
Asian Test Symposium 2000: 429- |
| 46 | EE | Chih-Wea Wang,
Chi-Feng Wu,
Jin-Fu Li,
Cheng-Wen Wu,
Tony Teng,
Kevin Chiu,
Hsiao-Ping Lin:
A built-in self-test and self-diagnosis scheme for embedded SRAM.
Asian Test Symposium 2000: 45-50 |
| 45 | EE | Jing-Reng Huang,
Chee-Kian Ong,
Kwang-Ting Cheng,
Cheng-Wen Wu:
An FPGA-based re-configurable functional tester for memory chips.
Asian Test Symposium 2000: 51-57 |
| 44 | EE | Juin-Ming Lu,
Cheng-Wen Wu:
Cost and Benefit Models for Logic and Memory BIST.
DATE 2000: 710-714 |
| 43 | EE | Chuang Cheng,
Chih-Tsun Huang,
Jing-Reng Huang,
Cheng-Wen Wu,
Chen-Jong Wey,
Ming-Chang Tsai:
BRAINS: A BIST Compiler for Embedded Memories.
DFT 2000: 299- |
| 42 | | Chi-Feng Wu,
Chih-Tsun Huang,
Chih-Wea Wang,
Kuo-Liang Cheng,
Cheng-Wen Wu:
Error Catch and Analysis for Semiconductor Memories Using March Tests.
ICCAD 2000: 468-471 |
| 41 | EE | Chi-Feng Wu,
Chih-Tsun Huang,
Kuo-Liang Cheng,
Cheng-Wen Wu:
Simulation-Based Test Algorithm Generation for Random Access Memories.
VTS 2000: 291-296 |
| 40 | EE | Kun-Jin Lin,
Cheng-Wen Wu:
A Low-Power CAM Design for LZ Data Compression.
IEEE Trans. Computers 49(10): 1139-1145 (2000) |
| 39 | EE | Jin-Hua Hong,
Chung-Hung Tsai,
Cheng-Wen Wu:
Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core.
IEEE Trans. VLSI Syst. 8(5): 503-516 (2000) |
| 38 | EE | Kun-Jin Lin,
Cheng-Wen Wu:
Testing content-addressable memories using functional fault modelsand march-like algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 577-588 (2000) |
| 37 | EE | Bin-Hong Lin,
Shao-Hui Shieh,
Cheng-Wen Wu:
A fast signature computation algorithm for LFSR and MISR.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1031-1040 (2000) |
| 36 | EE | Chih-Yuang Su,
Cheng-Wen Wu:
A Probabilistic Model for Path Delay Fault Testing.
J. Inf. Sci. Eng. 16(5): 783-794 (2000) |
| 1999 |
|---|
| 35 | EE | Chi-Feng Wu,
Cheng-Wen Wu:
Testing Interconnects of Dynamic Reconfigurable FPGAs.
ASP-DAC 1999: 279-282 |
| 34 | EE | Shyue-Kung Lu,
Tsung-Ying Lee,
Cheng-Wen Wu:
Defect Level Prediction Using Multi-Model Fault Coverage.
Asian Test Symposium 1999: 301- |
| 33 | EE | Chi-Feng Wu,
Chih-Tsun Huang,
Cheng-Wen Wu:
RAMSES: A Fast Memory Fault Simulator.
DFT 1999: 165-173 |
| 32 | EE | Jin-Fu Li,
Cheng-Wen Wu:
Testable and Fault Tolerant Design for FFT Networks.
DFT 1999: 201-209 |
| 31 | EE | Shyue-Kung Lu,
Cheng-Wen Wu:
A novel approach to testing LUT-based FPGAs.
ISCAS (1) 1999: 173-177 |
| 30 | EE | Chih-Tsun Huang,
Jing-Reng Huang,
Chi-Feng Wu,
Cheng-Wen Wu,
Tsin-Yuan Chang:
A Programmable BIST Core for Embedded DRAM.
IEEE Design & Test of Computers 16(1): 59-70 (1999) |
| 29 | | Wen-Feng Chang,
Cheng-Wen Wu:
Low-Cost Modular Totally Self-Checking Checker Design for m-out-of-n Code.
IEEE Trans. Computers 48(8): 815-826 (1999) |
| 28 | EE | Chih-Yuang Su,
Shih-Am Hwang,
Po-Song Chen,
Cheng-Wen Wu:
An improved Montgomery's algorithm for high-speed RSA public-key cryptosystem.
IEEE Trans. VLSI Syst. 7(2): 280-284 (1999) |
| 27 | EE | Wen-Feng Chang,
Cheng-Wen Wu:
TSC Berger-Code Checker Design for 2r-1-Bit Information.
J. Inf. Sci. Eng. 15(3): 429-440 (1999) |
| 26 | EE | Shih-Arn Hwang,
Cheng-Wen Wu:
Test Energy Minimization for C-Testable ILAs.
J. Inf. Sci. Eng. 15(6): 899-911 (1999) |
| 1998 |
|---|
| 25 | EE | Yu-Chun Chuang,
Cheng-Wen Wu:
On-Line Error Detection Schemes for a Systolic Finite-Field Inverter.
Asian Test Symposium 1998: 301-305 |
| 24 | EE | Cheng-Wen Wu:
Testing Embedded Memories: Is BIST the Ultimate Solution?.
Asian Test Symposium 1998: 516-517 |
| 23 | EE | Cheng-Wen Wu,
Chih-Yuang Su:
A Probabilistic Model for Path Delay Faults.
Asian Test Symposium 1998: 70-75 |
| 22 | EE | Yeong-Ruey Shieh,
Cheng-Wen Wu:
Control and Observation Structures for Analog Circuits.
IEEE Design & Test of Computers 15(2): 56-64 (1998) |
| 21 | EE | Shih-Arn Hwang,
Jin-Hua Hong,
Cheng-Wen Wu:
Sequential circuit fault simulation using logic emulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 724-736 (1998) |
| 1997 |
|---|
| 20 | EE | Cheng-Wen Wu:
On energy efficiency of VLSI testing.
Asian Test Symposium 1997: 132-137 |
| 19 | EE | Chih-Tsun Huang,
Cheng-Wen Wu:
High-speed C-testable systolic array design for Galois-field inversion.
ED&TC 1997: 342-346 |
| 18 | | Shyue-Kung Lu,
Sy-Yen Kuo,
Cheng-Wen Wu:
Fault-Tolerant Interleaved Memory Systems with Two-Level Redundancy.
IEEE Trans. Computers 46(9): 1028-1034 (1997) |
| 17 | EE | Wen-Feng Chang,
Cheng-Wen Wu:
Does There Exist a Combinational TSC Checker for 1/3 Code Using Only Primitive Gates?
J. Inf. Sci. Eng. 13(4): 681-695 (1997) |
| 1996 |
|---|
| 16 | EE | Bin-Hong Lin,
Shao-Hui Shieh,
Cheng-Wen Wu:
A MISR Computation Algorithm for Fast Signature Simulation.
Asian Test Symposium 1996: 213-218 |
| 15 | EE | Jin-Hua Hong,
Chung-Hung Tsai,
Cheng-Wen Wu:
Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module.
Asian Test Symposium 1996: 50-55 |
| 14 | EE | Shyue-Kung Lu,
Cheng-Wen Wu,
Ruei-Zong Hwang:
Cell delay fault testing for iterative logic arrays.
J. Electronic Testing 9(3): 311-316 (1996) |
| 1995 |
|---|
| 13 | EE | Yeong-Ruey Shieh,
Cheng-Wen Wu:
DC control and observation structures for analog circuits.
Asian Test Symposium 1995: 120-126 |
| 12 | EE | Shyue-Kung Lu,
Jen-Chuan Wang,
Cheng-Wen Wu:
C-testable design techniques for iterative logic arrays.
IEEE Trans. VLSI Syst. 3(1): 146-152 (1995) |
| 11 | EE | Yih-Lang Li,
Cheng-Wen Wu:
Cellular automata for efficient parallel logic and fault simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(6): 740-749 (1995) |
| 10 | EE | Cheng-Wen Wu,
Ming-Kwang Chang:
Bit-level systolic arrays for finite-field multiplications.
VLSI Signal Processing 10(1): 85-92 (1995) |
| 1994 |
|---|
| 9 | | Yih-Lang Li,
Cheng-Wen Wu:
Logic and Fault Simulation by Cellular Automata.
EDAC-ETC-EUROASIC 1994: 552-556 |
| 8 | | Cheng-Wen Wu,
Yung-Fa Chou:
General Modular Multiplication by Block Multiplication and Table Lookup.
ISCAS 1994: 295-298 |
| 7 | | Shih-Yuang Su,
Cheng-Wen Wu:
Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns.
IEEE Trans. Computers 43(4): 495-501 (1994) |
| 1993 |
|---|
| 6 | EE | Cheng-Wen Wu,
Jiann-Yuan Choue:
Fault-Tolerant FFT Butterfly Network Design.
J. Inf. Sci. Eng. 9(1): 137-150 (1993) |
| 1991 |
|---|
| 5 | | Cheng-Wen Wu,
Shyue-Kung Lu:
Designing Self-Testable Cellular Arrays.
ICCD 1991: 110-113 |
| 4 | EE | Kun-Jin Lin,
Cheng-Wen Wu:
Easily Testable Cellular Array Multipliers.
J. Inf. Sci. Eng. 7(3): 367-383 (1991) |
| 1990 |
|---|
| 3 | | Cheng-Wen Wu,
Peter R. Cappello:
Easily Testable Iterative Logic Arrays.
IEEE Trans. Computers 39(5): 640-652 (1990) |
| 2 | EE | Cheng-Wen Wu:
Relating Tiling and Coloring to Testing of Combinational Iterative Logic Arrays.
J. Inf. Sci. Eng. 6(1): 63-72 (1990) |
| 1987 |
|---|
| 1 | | Cheng-Wen Wu,
Peter R. Cappello:
Application-Specific CAD of High-Throughout IIR Filters.
COMPCON 1987: 302-305 |
