Wolfgang Kunz

2008
39	EE	Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Weber, Christian Jacobi, Matthias Pflanz: Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof. ASP-DAC 2008: 398-403
38	EE	Oliver Wienand, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Gert-Martin Greuel: An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths. CAV 2008: 473-486
37	EE	Evgeny Pavlenko, Markus Wedler, Dominik Stoffel, Wolfgang Kunz, Oliver Wienand, Evgeny Karibaev: Modeling of Custom-Designed Arithmetic Components for ABL Normalization. FDL 2008: 124-129
36	EE	Sacha Loitz, Markus Wedler, Christian Brehm, Timo Vogt, Norbert Wehn, Wolfgang Kunz: Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property Checking. SASP 2008: 48-54
35	EE	Minh D. Nguyen, Max Thalmaier, Markus Wedler, J. Bormann, Dominik Stoffel, Wolfgang Kunz: Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants. IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2068-2082 (2008)
2007
34	EE	Markus Wedler, Dominik Stoffel, Raik Brinkmann, Wolfgang Kunz: A Normalization Method for Arithmetic Data-Path Verification. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1909-1922 (2007)
2005
33	EE	Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Normalization at the arithmetic bit level. DAC 2005: 457-462
32		Minh D. Nguyen, Dominik Stoffel, Wolfgang Kunz: Enhancing BMC-based Protocol Verification Using Transition-By-Transition FSM Traversal. GI Jahrestagung (1) 2005: 303-307
31		Minh D. Nguyen, Dominik Stoffel, Markus Wedler, Wolfgang Kunz: Transition-by-transition FSM traversal for reachability analysis in bounded model checking. ICCAD 2005: 1068-1075
2004
30	EE	Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Exploiting state encoding for invariant generation in induction-based property checking. ASP-DAC 2004: 424-429
29	EE	Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Arithmetic Reasoning in DPLL-Based SAT Solving. DATE 2004: 30-35
28	EE	Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz: Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. ICCD 2004: 350-353
27	EE	Dominik Stoffel, Wolfgang Kunz: Equivalence checking of arithmetic circuits on the arithmetic bit level. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 586-597 (2004)
26	EE	Dominik Stoffel, Markus Wedler, Peter Warkentin, Wolfgang Kunz: Structural FSM traversal. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 598-619 (2004)
2003
25	EE	Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Using RTL Statespace Information and State Encoding for Induction Based Property Checking. DATE 2003: 11156-11157
24	EE	Ingmar Neumann, Wolfgang Kunz: Layout driven retiming using the coupled edge timing model. IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 825-835 (2003)
2002
23	EE	Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Lukas VanGinneken: Improving Placement under the Constant Delay Model. DATE 2002: 677-682
22	EE	Armin Biere, Wolfgang Kunz: SAT and ATPG: Boolean engines for formal hardware verification. ICCAD 2002: 782-785
21	EE	Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz: Accelerating Retiming Under the Coupled-Edge Timing Model. ISVLSI 2002: 135-140
20	EE	Markus Wedler, Dominik Stoffel, Wolfgang Kunz: Improving Structural FSM Traversal by Constraint-Satisfying Logic Simulation. ISVLSI 2002: 151-158
2001
19	EE	Dominik Stoffel, Wolfgang Kunz: Verification of Integer Multipliers on the Arithmetic Bit Level. ICCAD 2001: 183-189
18	EE	Ingmar Neumann, Wolfgang Kunz: Placement Driven Retiming with a Coupled Edge Timing Model. ICCAD 2001: 95-102
17	EE	Ingmar Neumann, Wolfgang Kunz: Tight coupling of timing-driven placement and retiming. ISCAS (5) 2001: 351-354
16	EE	Hendrik Hartje, Ingmar Neumann, Dominik Stoffel, Wolfgang Kunz: Cycle time optimization by timing driven placement with simultaneous netlist transformations. ISCAS (5) 2001: 359-362
15	EE	Kolja Sulimma, Wolfgang Kunz: An exact algorithm for solving difficult detailed routing problems. ISPD 2001: 198-203
1999
14		Kolja Sulimma, Dominik Stoffel, Wolfgang Kunz: Accelerating Boolean Implications with FPGAs. FPL 1999: 532-537
13	EE	Ingmar Neumann, Dominik Stoffel, Hendrik Hartje, Wolfgang Kunz: Cell replication and redundancy elimination during placement for cycle time optimization. ICCAD 1999: 25-30
1998
12	EE	Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz: LOT: Logic Optimization with Testability. New transformations for logic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 386-399 (1998)
1997
11	EE	Dominik Stoffel, Wolfgang Kunz: Record & play: a structural fixed point iteration for sequential circuit verification. ICCAD 1997: 394-399
10	EE	Wolfgang Kunz, Dominik Stoffel, Premachandran R. Menon: Logic optimization and equivalence checking by implication analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 266-281 (1997)
1996
9	EE	Dhiraj K. Pradhan, Mitrajit Chatterjee, Madhu V. Swarna, Wolfgang Kunz: Gate-level synthesis for low-power using new transformations. ISLPED 1996: 297-300
8	EE	Wolfgang Kunz, Dhiraj K. Pradhan, Sudhakar M. Reddy: A novel framework for logic verification in a synthesis environment. IEEE Trans. on CAD of Integrated Circuits and Systems 15(1): 20-32 (1996)
1995
7		Subodh M. Reddy, Wolfgang Kunz, Dhiraj K. Pradhan: Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment. DAC 1995: 414-419
6	EE	Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz: LOT: logic optimization with testability-new transformations using recursive learning. ICCAD 1995: 318-325
1994
5	EE	Wolfgang Kunz, Premachandran R. Menon: Multi-level logic optimization by implication analysis. ICCAD 1994: 6-13
4	EE	Wolfgang Kunz, Dhiraj K. Pradhan: Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 13(9): 1143-1158 (1994)
1993
3	EE	Wolfgang Kunz: HANNIBAL: an efficient tool for logic verification based on recursive learning. ICCAD 1993: 538-543
2	EE	Wolfgang Kunz, Dhiraj K. Pradhan: Accelerated dynamic learning for test pattern generation in combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 684-694 (1993)
1992
1		Wolfgang Kunz, Dhiraj K. Pradhan: Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits. ITC 1992: 816-825

Coauthor Index

1	Michel R. C. M. Berkelaar	[28]
2	Armin Biere	[22]
3	J. Bormann	[35]
4	Christian Brehm	[36]
5	Raik Brinkmann	[34]
6	Mitrajit Chatterjee	[6] [9] [12]
7	Gert-Martin Greuel	[38]
8	Hendrik Hartje	[13] [16]
9	Christian Jacobi	[39]
10	Evgeny Karibaev	[37]
11	Udo Krautz	[39]
12	Sacha Loitz	[36]
13	Premachandran R. Menon	[5] [10]
14	Ingmar Neumann	[13] [16] [17] [18] [21] [23] [24] [28]
15	Minh D. Nguyen	[31] [32] [35]
16	Evgeny Pavlenko	[37]
17	Matthias Pflanz	[39]
18	Dhiraj K. Pradhan	[1] [2] [4] [6] [7] [8] [9] [12]
19	Subodh M. Reddy	[7]
20	Sudhakar M. Reddy	[8]
21	Dominik Stoffel	[10] [11] [13] [14] [16] [19] [20] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [37] [38]
22	Kolja Sulimma	[14] [15] [21] [23] [28]
23	Madhu V. Swarna	[9]
24	Max Thalmaier	[35]
25	Lukas VanGinneken	[23]
26	Timo Vogt	[36]
27	Peter Warkentin	[26]
28	Kai Weber	[39]
29	Markus Wedler	[20] [25] [26] [29] [30] [31] [33] [34] [35] [36] [37] [38] [39]
30	Norbert Wehn	[36]
31	Oliver Wienand	[37] [38]

Colors in the list of coauthors