2009 |
63 | EE | Nilanjan Mukherjee,
Janusz Rajski,
Jerzy Tyszer:
Defect Aware to Power Conscious Tests - The New DFT Landscape.
VLSI Design 2009: 23-25 |
62 | EE | Nilanjan Mukherjee,
Artur Pogiel,
Janusz Rajski,
Jerzy Tyszer:
High-Speed On-Chip Event Counters for Embedded Systems.
VLSI Design 2009: 275-280 |
2008 |
61 | EE | Janusz Rajski,
Jerzy Tyszer,
Grzegorz Mrugalski,
Wu-Tung Cheng,
Neelanjan Mukherjee,
Mark Kassab:
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 147-159 (2008) |
60 | EE | Dariusz Czysz,
Grzegorz Mrugalski,
Janusz Rajski,
Jerzy Tyszer:
Low-Power Test Data Application in EDT Environment Through Decompressor Freeze.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1278-1290 (2008) |
2007 |
59 | EE | Grzegorz Mrugalski,
Janusz Rajski,
Dariusz Czysz,
Jerzy Tyszer:
New Test Data Decompressor for Low Power Applications.
DAC 2007: 539-544 |
58 | EE | Dariusz Czysz,
Grzegorz Mrugalski,
Janusz Rajski,
Jerzy Tyszer:
Low Power Embedded Deterministic Test.
VTS 2007: 75-83 |
57 | EE | Jerzy Tyszer,
Janusz Rajski,
Grzegorz Mrugalski,
Nilanjan Mukherjee,
Mark Kassab,
Wu-Tung Cheng,
Manish Sharma,
Liyang Lai:
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis.
IEEE Design & Test of Computers 24(5): 476-485 (2007) |
56 | EE | Grzegorz Mrugalski,
Artur Pogiel,
Janusz Rajski,
Jerzy Tyszer:
Fault Diagnosis With Convolutional Compactors.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1478-1494 (2007) |
55 | EE | Grzegorz Mrugalski,
Janusz Rajski,
Chen Wang,
Artur Pogiel,
Jerzy Tyszer:
Isolation of Failing Scan Cells through Convolutional Test Response Compaction.
J. Electronic Testing 23(1): 35-45 (2007) |
2006 |
54 | EE | Grzegorz Mrugalski,
Janusz Rajski,
Jerzy Tyszer:
Test response compactor with programmable selector.
DAC 2006: 1089-1094 |
53 | EE | Artur Pogiel,
Janusz Rajski,
Jerzy Tyszer:
Convolutional Compactors with Variable Polynomials.
European Test Symposium 2006: 117-122 |
52 | EE | Grzegorz Mrugalski,
Nilanjan Mukherjee,
Janusz Rajski,
Jerzy Tyszer:
High Performance Dense Ring Generators.
IEEE Trans. Computers 55(1): 83-87 (2006) |
2005 |
51 | EE | Huaxing Tang,
Chen Wang,
Janusz Rajski,
Sudhakar M. Reddy,
Jerzy Tyszer,
Irith Pomeranz:
On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios.
VLSI Design 2005: 59-64 |
50 | EE | Janusz Rajski,
Jerzy Tyszer:
Synthesis of X-Tolerant Convolutional Compactors.
VTS 2005: 114-119 |
49 | EE | Janusz Rajski,
Jerzy Tyszer,
Chen Wang,
Sudhakar M. Reddy:
Finite memory test response compactors for embedded test applications.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 622-634 (2005) |
2004 |
48 | EE | Grzegorz Mrugalski,
Chen Wang,
Artur Pogiel,
Jerzy Tyszer,
Janusz Rajski:
Fault Diagnosis in Designs with Convolutional Compactors.
ITC 2004: 498-507 |
47 | EE | Janusz Rajski,
Nilanjan Mukherjee,
Jerzy Tyszer,
Thomas Rinderknecht:
Embedded Test for Low Cost Manufacturing.
VLSI Design 2004: 21-23 |
46 | EE | Grzegorz Mrugalski,
Nilanjan Mukherjee,
Janusz Rajski,
Jerzy Tyszer:
Planar High Performance Ring Generators.
VTS 2004: 193-198 |
45 | EE | Janusz Rajski,
Jerzy Tyszer,
Mark Kassab,
Nilanjan Mukherjee:
Embedded deterministic test.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 776-792 (2004) |
44 | EE | Grzegorz Mrugalski,
Janusz Rajski,
Jerzy Tyszer:
Ring generators - new devices for embedded test applications.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1306-1320 (2004) |
2003 |
43 | EE | Chen Wang,
Sudhakar M. Reddy,
Irith Pomeranz,
Janusz Rajski,
Jerzy Tyszer:
On Compacting Test Response Data Containing Unknown Values.
ICCAD 2003: 855-862 |
42 | EE | Janusz Rajski,
Jerzy Tyszer:
Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs.
ICCD 2003: 331- |
41 | EE | Janusz Rajski,
Jerzy Tyszer,
Chen Wang,
Sudhakar M. Reddy:
Convolutional Compaction of Test Responses.
ITC 2003: 745-754 |
40 | EE | Grzegorz Mrugalski,
Janusz Rajski,
Jerzy Tyszer:
High Speed Ring Generators and Compactors of Test Data.
VTS 2003: 57-62 |
39 | EE | Grzegorz Mrugalski,
Jerzy Tyszer,
Janusz Rajski:
2D Test Sequence Generators.
IEEE Design & Test of Computers 20(1): 51-59 (2003) |
38 | EE | Janusz Rajski,
Mark Kassab,
Nilanjan Mukherjee,
Nagesh Tamarapalli,
Jerzy Tyszer,
Jun Qian:
Embedded Deterministic Test for Low-Cost Manufacturing.
IEEE Design & Test of Computers 20(5): 58-66 (2003) |
37 | EE | Janusz Rajski,
Jerzy Tyszer:
Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients.
J. Electronic Testing 19(6): 645-657 (2003) |
2002 |
36 | EE | Janusz Rajski,
Jerzy Tyszer,
Mark Kassab,
Nilanjan Mukherjee,
Rob Thompson,
Kun-Han Tsai,
Andre Hertwig,
Nagesh Tamarapalli,
Grzegorz Mrugalski,
Geir Eide,
Jun Qian:
Embedded Deterministic Test for Low-Cost Manufacturing Test.
ITC 2002: 301-310 |
2001 |
35 | EE | Nilanjan Mukherjee,
Janusz Rajski,
Jerzy Tyszer:
Testing Schemes for FIR Filter Structures.
IEEE Trans. Computers 50(7): 674-688 (2001) |
2000 |
34 | EE | Grzegorz Mrugalski,
Jerzy Tyszer,
Janusz Rajski:
Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators.
VTS 2000: 377-388 |
33 | EE | Janusz Rajski,
Nagesh Tamarapalli,
Jerzy Tyszer:
Automated synthesis of phase shifters for built-in self-testapplications.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1175-1188 (2000) |
32 | EE | Grzegorz Mrugalski,
Janusz Rajski,
Jerzy Tyszer:
Cellular automata-based test pattern generators with phase shifters.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 878-893 (2000) |
1999 |
31 | | Grzegorz Mrugalski,
Jerzy Tyszer,
Janusz Rajski:
Synthesis of pattern generators based on cellular automata with phase shifters.
ITC 1999: 368-377 |
30 | | Janusz Rajski,
Jerzy Tyszer,
Sanjay Patel:
Built-In Self-Test for Systems on Silicon.
VLSI Design 1999: 609-610 |
29 | EE | Janusz Rajski,
Grzegorz Mrugalski,
Jerzy Tyszer:
Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters.
VTS 1999: 236-245 |
28 | | Janusz Rajski,
Jerzy Tyszer:
Diagnosis of Scan Cells in BIST Environment.
IEEE Trans. Computers 48(7): 724-731 (1999) |
1998 |
27 | EE | Janusz Rajski,
Nagesh Tamarapalli,
Jerzy Tyszer:
Automated synthesis of large phase shifters for built-in self-test.
ITC 1998: 1047-1056 |
26 | EE | Janusz Rajski,
Jerzy Tyszer:
Modular logic built-in self-test for IP cores.
ITC 1998: 313- |
25 | EE | Janusz Rajski,
Jerzy Tyszer:
Design of Phase Shifters for BIST Applications.
VTS 1998: 218-224 |
24 | | Janusz Rajski,
Jerzy Tyszer,
Nadime Zacharia:
Test Data Decompression for Multiple Scan Designs with Boundary Scan.
IEEE Trans. Computers 47(11): 1188-1200 (1998) |
1997 |
23 | | Nilanjan Mukherjee,
Janusz Rajski,
Jerzy Tyszer:
Parameterizable Testing Scheme for FIR Filters.
ITC 1997: 694-703 |
22 | | Janusz Rajski,
Jerzy Tyszer:
Fault Diagnosis in Scan-Based BIST.
ITC 1997: 894-902 |
21 | | Nilanjan Mukherjee,
Janusz Rajski,
Jerzy Tyszer:
Design of Testable Multipliers for Fixed-Width Data Paths.
IEEE Trans. Computers 46(7): 795-810 (1997) |
20 | EE | Katarzyna Radecka,
Janusz Rajski,
Jerzy Tyszer:
Arithmetic built-in self-test for DSP cores.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1358-1369 (1997) |
1996 |
19 | | Nadime Zacharia,
Janusz Rajski,
Jerzy Tyszer,
John A. Waicukauski:
Two-Dimensional Test Data Decompressor for Multiple Scan Designs.
ITC 1996: 186-194 |
18 | | Andrzej Jajszczyk,
Jerzy Tyszer:
Broadband Time-Division Circuit Switching.
IEEE Journal on Selected Areas in Communications 14(2): 337-345 (1996) |
17 | | Janusz Rajski,
Jerzy Tyszer:
On Linear Dependencies in Subspaces of LFSR-Generated Sequences.
IEEE Trans. Computers 45(10): 1212-1216 (1996) |
16 | | Sanjay Gupta,
Janusz Rajski,
Jerzy Tyszer:
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns.
IEEE Trans. Computers 45(8): 939-949 (1996) |
1995 |
15 | EE | Mark Kassab,
Nilanjan Mukherjee,
Janusz Rajski,
Jerzy Tyszer:
Software Accelerated Functional Fault Simulation for Data-Path Architectures.
DAC 1995: 333-338 |
14 | EE | Nilanjan Mukherjee,
Janusz Rajski,
Jerzy Tyszer:
On testable multipliers for fixed-width data path architectures.
ICCAD 1995: 541-547 |
13 | | Mark Kassab,
Janusz Rajski,
Jerzy Tyszer:
Hierarchical Functional-Fault Simulation for High-Level Synthesis.
ITC 1995: 596-605 |
12 | EE | Nilanjan Mukherjee,
H. Kassab,
Janusz Rajski,
Jerzy Tyszer:
Arithmetic built-in self test for high-level synthesis.
VTS 1995: 132-139 |
11 | EE | Nadime Zacharia,
Janusz Rajski,
Jerzy Tyszer:
Decompression of test data using variable-length seed LFSRs.
VTS 1995: 426-433 |
1994 |
10 | EE | Sanjay Gupta,
Janusz Rajski,
Jerzy Tyszer:
Test pattern generation based on arithmetic operations.
ICCAD 1994: 117-124 |
1993 |
9 | | Janusz Rajski,
Jerzy Tyszer:
Recursive Pseudoexhaustive Test Pattern Generation.
IEEE Trans. Computers 42(12): 1517-1521 (1993) |
8 | | Janusz Rajski,
Jerzy Tyszer:
Accumulator-Based Compaction of Test Responses.
IEEE Trans. Computers 42(6): 643-650 (1993) |
7 | EE | Janusz Rajski,
Jerzy Tyszer:
Test responses compaction in accumulators with rotate carry adders.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(4): 531-539 (1993) |
1991 |
6 | EE | Janusz Rajski,
Jerzy Tyszer:
On the diagnostic properties of linear feedback shift registers.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(10): 1316-1322 (1991) |
1990 |
5 | | Janusz Rajski,
Jerzy Tyszer,
Babak Salimi:
On the Diagnostic Resolution of Signature Analysis.
ICCAD 1990: 364-367 |
1988 |
4 | | Jerzy Tyszer:
A Multiple Fault-Tolerant Processor Network Architecture for Pipeline Computing.
IEEE Trans. Computers 37(11): 1414-1418 (1988) |
1986 |
3 | | Janusz Rajski,
Jerzy Tyszer:
The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's.
IEEE Trans. Computers 35(1): 81-85 (1986) |
1985 |
2 | | Janusz Rajski,
Jerzy Tyszer:
Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays.
IEEE Trans. Computers 34(6): 549-553 (1985) |
1984 |
1 | | Janusz Rajski,
Jerzy Tyszer:
The detection of small size multiple faults by single fault test sets n programmable logic arrays.
Fehlertolerierende Rechensysteme 1984: 417-425 |