| 2008 |
|---|
| 8 | EE | Saihua Lin,
Yu Wang,
Rong Luo,
Huazhong Yang:
A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application.
ASP-DAC 2008: 304-309 |
| 7 | EE | Saihua Lin,
Huazhong Yang,
Rong Luo:
A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems.
IEEE Trans. VLSI Syst. 16(10): 1372-1384 (2008) |
| 2007 |
|---|
| 6 | EE | Saihua Lin,
Huazhong Yang,
Rong Luo:
A Novel Low Power Interface Circuit Design Technique for Multiple Voltage Islands Scheme.
ISCAS 2007: 1401-1404 |
| 5 | EE | Saihua Lin,
Huazhong Yang,
Rong Luo:
High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit.
ISVLSI 2007: 273-278 |
| 4 | EE | Saihua Lin,
Huazhong Yang,
Rong Luo:
A Novel gamma d/n, RLCG Transmission Line Model Considering Complex RC(L) Loads.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 970-977 (2007) |
| 2006 |
|---|
| 3 | EE | Saihua Lin,
Rong Luo,
Huazhong Yang,
Hui Wang:
A 0.9V 10GHz 71µW Static D Flip-flop by using FinFET Devices.
APCCAS 2006: 1795-1798 |
| 2 | EE | Saihua Lin,
Hongli Gao,
Huazhong Yang:
Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS.
PATMOS 2006: 486-495 |
| 1 | EE | Saihua Lin,
Huazhong Yang:
Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling.
PATMOS 2006: 504-513 |
