Hamid Mahmoodi

Hamid Mahmoodi-Meimand

2009
40	EE	Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Ali Peiravi, Snorre Aunet, Tuan Vu Cao: New subthreshold concepts in 65nm CMOS technology. ISQED 2009: 162-166
2008
39	EE	Farshad Moradi, Dag T. Wisland, Snorre Aunet, Hamid Mahmoodi, Tuan Vu Cao: 65NM sub-threshold 11T-SRAM for ultra low voltage applications. SoCC 2008: 113-118
38	EE	Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy: Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 174-183 (2008)
37	EE	Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy: Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. J. Electronic Testing 24(6): 577-590 (2008)
2007
36	EE	Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia: Low-overhead design technique for calibration of maximum frequency at multiple operating points. ICCAD 2007: 401-404
35	EE	Vishwanadh Tirumalashetty, Hamid Mahmoodi: Clock Gating and Negative Edge Triggering for Energy Recovery Clock. ISCAS 2007: 1141-1144
34	EE	Keejong Kim, Hamid Mahmoodi, Kaushik Roy: A low-power SRAM using bit-line charge-recycling technique. ISLPED 2007: 177-182
33	EE	Rajani Kuchipudi, Hamid Mahmoodi: Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS. ISQED 2007: 27-32
32	EE	Animesh Datta, Ashish Goel, R. T. Cakici, Hamid Mahmoodi, D. Lekshmanan, Kaushik Roy: Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1957-1966 (2007)
2006
31	EE	Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy: Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. ASP-DAC 2006: 665-670
30	EE	Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia: Low power synthesis of dynamic logic circuits using fine-grained clock gating. DATE 2006: 862-867
29	EE	Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici: Double-Gate SOI Devices for Low-Power and High-Performance Applications. VLSI Design 2006: 445-452
28	EE	Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. IEEE Trans. VLSI Syst. 14(2): 183-192 (2006)
27	EE	Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi: Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. IEEE Trans. VLSI Syst. 14(9): 1034-1039 (2006)
2005
26	EE	Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy: Energy recovery clocked dynamic logic. ACM Great Lakes Symposium on VLSI 2005: 468-471
25	EE	Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peiravi: A high speed and leakage-tolerant domino logic for high fan-in gates. ACM Great Lakes Symposium on VLSI 2005: 478-481
24	EE	Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy: Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. Asian Test Symposium 2005: 176-181
23	EE	Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy: A novel synthesis approach for active leakage power reduction using dynamic supply gating. DAC 2005: 479-484
22	EE	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy: A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. DATE 2005: 1136-1141
21		Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici: Double-gate SOI devices for low-power and high-performance applications. ICCAD 2005: 217-224
20	EE	Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy: Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. ICCD 2005: 206-214
19	EE	Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy: Process Variation Tolerant Online Current Monitor for Robust Systems. IOLTS 2005: 171-176
18	EE	Aliakbar Ghadiri, Hamid Mahmoodi-Meimand: Pre-capturing static pulsed flip-flops. ISCAS (3) 2005: 2421-2424
17	EE	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy: Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. ISQED 2005: 453-458
16	EE	Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. ISQED 2005: 490-495
15	EE	Aliakbar Ghadiri, Hamid Mahmoodi-Meimand: Dual-Edge Triggered Static Pulsed Flip-Flops. VLSI Design 2005: 846-849
14	EE	Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy: Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. VTS 2005: 292-297
13	EE	Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy: A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Trans. VLSI Syst. 13(1): 27-38 (2005)
12	EE	Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy: Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. IEEE Trans. VLSI Syst. 13(11): 1286-1295 (2005)
11	EE	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy: Low-power scan design using first-level supply gating. IEEE Trans. VLSI Syst. 13(3): 384-395 (2005)
10	EE	Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1859-1880 (2005)
2004
9	EE	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy: First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. DFT 2004: 314-315
8	EE	Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy: Statistical design and optimization of SRAM cell for yield enhancement. ICCAD 2004: 10-13
7	EE	Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy: A Novel Low-Power Scan Design Technique Using Supply Gating. ICCD 2004: 60-65
6		Hamid Mahmoodi-Meimand, Kaushik Roy: Dual-edge triggered level converting flip-flops. ISCAS (2) 2004: 661-664
5		Hamid Mahmoodi-Meimand, Kaushik Roy: Data-retention flip-flops for power-down applications. ISCAS (2) 2004: 677-680
2003
4	EE	Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy: Energy recovery clocking scheme and flip-flops for ultra low-energy applications. ISLPED 2003: 54-59
2002
3	EE	Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy: High performance and low power FIR filter design based on sharing multiplication. ISLPED 2002: 295-300
2	EE	Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand: Leakage Current in Deep-Submicron CMOS Circuits. Journal of Circuits, Systems, and Computers 11(6): 575-600 (2002)
2001
1	EE	Hamid Mahmoodi-Meimand, Ali Afzali-Kusha: Efficient power clock generation for adiabatic logic. ISCAS (4) 2001: 642-645

Coauthor Index

1	Ali Afzali-Kusha	[1]
2	Amit Agarwal	[13]
3	Hari Ananthan	[21] [29]
4	Snorre Aunet	[39] [40]
5	Nilanjan Banerjee	[20] [23] [27] [30]
6	Aditya Bansal	[21] [29]
7	Swarup Bhunia	[7] [9] [11] [12] [14] [17] [20] [22] [23] [27] [30] [31] [36] [37]
8	R. T. Cakici	[32]
9	Tamer Cakici	[21] [29]
10	Tuan Vu Cao	[39] [40]
11	Qikai Chen	[12] [14] [19] [23] [26]
12	Hunsoo Choo	[3]
13	Matthew Cooke	[4] [26]
14	Animesh Datta	[13] [32]
15	Aliakbar Ghadiri	[15] [18]
16	Debjyoti Ghosh	[7] [11] [17]
17	Ashish Goel	[31] [32]
18	Woopyo Jeong	[3]
19	Keejong Kim	[34]
20	Sivasubramaniam Krishnamurthy	[36]
21	Rajani Kuchipudi	[33]
22	D. Lekshmanan	[32]
23	Farshad Moradi	[25] [39] [40]
24	Saibal Mukhopadhyay	[2] [7] [8] [10] [11] [16] [19] [21] [24] [28] [29] [38]
25	Jongsun Park	[3]
26	Bipul Chandra Paul (Bipul C. Paul)	[13]
27	Somnath Paul	[36]
28	Ali Peiravi	[25] [40]
29	Arijit Raychowdhury	[9] [20] [22] [24] [27] [37]
30	Kaushik Roy	[2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [16] [17] [19] [20] [21] [22] [23] [24] [26] [27] [28] [29] [30] [31] [32] [34] [37] [38]
31	Vishwanadh Tirumalashetty	[35]
32	Yongtao Wang	[3]
33	Dag T. Wisland	[39] [40]

Colors in the list of coauthors