| 2008 |
|---|
| 7 | EE | Tai-Chen Chen,
Guang-Wan Liao,
Yao-Wen Chang:
Predictive formulae for OPC with applications to lithography-friendly routing.
DAC 2008: 510-515 |
| 2007 |
|---|
| 6 | EE | Chung-Wei Lin,
Ming-Chao Tsai,
Kuang-Yao Lee,
Tai-Chen Chen,
Ting-Chi Wang,
Yao-Wen Chang:
Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability.
ASP-DAC 2007: 238-243 |
| 5 | EE | Tai-Chen Chen,
Yao-Wen Chang:
Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1041-1053 (2007) |
| 2006 |
|---|
| 4 | EE | Tai-Chen Chen,
Yao-Wen Chang,
Shyh-Chang Lin:
A novel framework for multilevel full-chip gridless routing.
ASP-DAC 2006: 636-641 |
| 2005 |
|---|
| 3 | EE | Tai-Chen Chen,
Yao-Wen Chang:
Multilevel full-chip gridless routing considering optical proximity correction.
ASP-DAC 2005: 1160-1163 |
| 2004 |
|---|
| 2 | | Tai-Chen Chen,
Song-Ra Pan,
Yao-Wen Chang:
Timing modeling and optimization under the transmission line model.
IEEE Trans. VLSI Syst. 12(1): 28-41 (2004) |
| 2001 |
|---|
| 1 | | Tai-Chen Chen,
Song-Ra Pan,
Yao-Wen Chang:
Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model.
ICCD 2001: 192-198 |
