Resve A. Saleh

Resve Saleh, Res Saleh

2009
62	EE	Xiongfei Meng, Resve A. Saleh: Active decap design considerations for optimal supply noise reduction. ISQED 2009: 765-769
61	EE	Sohaib Majzoub, Resve Saleh, Rabab Ward: PVT variation impact on voltage island formation in MPSoC design. ISQED 2009: 814-819
60	EE	Dipanjan Sengupta, Resve A. Saleh: Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip Design. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 316-326 (2009)
2008
59	EE	Dipanjan Sengupta, Resve A. Saleh: Application-driven floorplan-aware voltage island design. DAC 2008: 155-160
58	EE	Tatsuya Koyagi, Masahiro Fukui, Resve Saleh: Delay macromodeling and estimation for RTL. ISCAS 2008: 2430-2433
57	EE	Zahra Sadat Ebadi, Resve A. Saleh: A Fully-Integrated 2.4 GHz Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOS. ISQED 2008: 411-416
56	EE	Jeff Mueller, Resve A. Saleh: A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks. ISQED 2008: 572-577
55	EE	Uthman Alsaiari, Resve A. Saleh: Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits. ISQED 2008: 798-803
54	EE	Dipanjan Sengupta, Resve A. Saleh: Supply voltage selection in Voltage Island based SoC design. SoCC 2008: 219-222
53	EE	Jeff Mueller, Resve Saleh: Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance. VLSI Design 2008: 214-219
52	EE	Xiongfei Meng, Resve A. Saleh, Karim Arabi: Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS. IEEE Trans. VLSI Syst. 16(11): 1581-1588 (2008)
51	EE	Peter Hallschmid, Resve Saleh: Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 508-515 (2008)
2007
50	EE	Peter Hallschmid, Resve Saleh: Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling. DAC 2007: 732-737
49	EE	Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve Saleh: Essential Fault-Tolerance Metrics for NoC Infrastructures. IOLTS 2007: 37-42
48	EE	Xiongfei Meng, Karim Arabi, Resve Saleh: A Novel Active Decoupling Capacitor Design in 90nm CMOS. ISCAS 2007: 657-660
47	EE	Amit Kedia, Resve Saleh: Power Reduction of On-Chip Serial Links. ISCAS 2007: 865-868
46	EE	Resve Saleh, Pallab K. Chatterjee, Ivan Pesic, Robbert Dobkins, Mike Smayling, Joseph Sawicki: DFM-EDA's Salvation or its Excuse for Being out of Touch with Engineering? ISQED 2007: 7-8
45	EE	Uthman Alsaiari, Resve Saleh: Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy. ISQED 2007: 703-710
44	EE	Karim Arabi, Resve A. Saleh, Xiongfei Meng: Power Supply Noise in SoCs: Metrics, Management, and Measurement. IEEE Design & Test of Computers 24(3): 236-244 (2007)
43	EE	Dipanjan Sengupta, Resve Saleh: Generalized Power-Delay Metrics in Deep Submicron CMOS Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 183-189 (2007)
42	EE	Cristian Grecu, André Ivanov, Resve A. Saleh, Partha Pratim Pande: Testing Network-on-Chip Communication Fabrics. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2201-2214 (2007)
41	EE	Zahra Sadat Ebadi, Alireza Nasiri Avanaki, Resve Saleh, André Ivanov: Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip. Integration 40(2): 149-160 (2007)
2006
40	EE	Cristian Grecu, André Ivanov, Res Saleh, Partha Pratim Pande: NoC Interconnect Yield Improvement Using Crosspoint Redundancy. DFT 2006: 457-465
39	EE	Cristian Grecu, André Ivanov, Res Saleh, Egor S. Sogomonyan, Partha Pratim Pande: On-line Fault Detection and Location for NoC Interconnects. IOLTS 2006: 145-150
38	EE	Reza Molavi, Shahriar Mirabbasi, Resve A. Saleh: A high-speed low-energy dynamic PLA using an input-isolation scheme. ISCAS 2006
37	EE	Uthman Alsaiari, Resve Saleh: Testable and self-repairable structured logic design. ISCAS 2006
36	EE	Xiongfei Meng, Resve A. Saleh, Karim Arabi: Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology. ISQED 2006: 266-271
35	EE	Victor Aken Ova, Resve Saleh: A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm. ISVLSI 2006: 103-108
34	EE	Peter Hallschmid, Resve Saleh: Fast Configuration of an Energy-Efficient Branch Predictor. ISVLSI 2006: 289-294
33	EE	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh: BIST for Network-on-Chip Interconnect Infrastructures. VTS 2006: 30-35
2005
32	EE	Cristian Grecu, Partha Pratim Pande, Baosheng Wang, André Ivanov, Res Saleh: Methodologies and Algorithms for Testing Switch-Based NoC Interconnects. DFT 2005: 238-246
31	EE	Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Res Saleh: Effect of traffic localization on energy dissipation in NoC-based interconnect. ISCAS (2) 2005: 1774-1777
30	EE	Dipanjan Sengupta, Resve A. Saleh: Power-Delay Metrics Revisited for 90nm CMOS Technology. ISQED 2005: 291-296
29	EE	Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli: Design, Synthesis, and Test of Networks on Chips. IEEE Design & Test of Computers 22(5): 404-413 (2005)
28	EE	Resve A. Saleh: An approach that will NoC your SoCs off! IEEE Design & Test of Computers 22(5): 488 (2005)
27	EE	Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh: Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures. IEEE Trans. Computers 54(8): 1025-1040 (2005)
26	EE	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh: Timing analysis of network on chip architectures for MP-SoC platforms. Microelectronics Journal 36(9): 833-845 (2005)
2004
25	EE	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh: Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs. ACM Great Lakes Symposium on VLSI 2004: 192-195
24	EE	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh: A Scalable Communication-Centric SoC Interconnect Architecture. ISQED 2004: 343-348
2003
23	EE	S. Shang, Shahriar Mirabbasi, Resve A. Saleh: A technique for DC-offset removal and carrier phase error compensation in integrated wireless receivers. ISCAS (1) 2003: 173-176
22	EE	Mama Hamour, Resve A. Saleh, Shahriar Mirabbasi, André Ivanov: Analog IP design flow for SoC applications. ISCAS (4) 2003: 676-679
21	EE	Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh: Design of a switch for network on chip applications. ISCAS (5) 2003: 217-220
2002
20	EE	Resve A. Saleh, G. Lim, T. Kadowaki, K. Uchiyama: Trends in Low Power Digital System-on-Chip Designs (invited). ISQED 2002: 373-
19	EE	Mohsen Nahvi, André Ivanov, Resve A. Saleh: Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores. ITC 2002: 1176-1184
2000
18	EE	Resve A. Saleh, Syed Zakir Hussain, Steffen Rochel, David Overhauser: Clock skew verification in the presence of IR-drop in the powerdistribution network. IEEE Trans. on CAD of Integrated Circuits and Systems 19(6): 635-644 (2000)
1998
17	EE	Resve A. Saleh, David Overhauser, Sandy Taylor: Full-chip verification of UDSM designs. ICCAD 1998: 453-460
1996
16	EE	Resve A. Saleh, Brian A. A. Antao, Jaidip Singh: Multilevel and mixed-domain simulation of analog circuits and systems. IEEE Trans. on CAD of Integrated Circuits and Systems 15(1): 68-82 (1996)
15	EE	J. G. Mueller, Brian A. A. Antao, Resve A. Saleh: A multifrequency technique for frequency response computation with application to switched-capacitor circuits with nonlinearities. IEEE Trans. on CAD of Integrated Circuits and Systems 15(7): 775-790 (1996)
1995
14		Yen-Cheng Wen, Kyle Gallivan, Resve A. Saleh: Improving Parallel Circuit Simulation Using High-Level Waveforms. ISCAS 1995: 728-731
1993
13	EE	Gih-Guang Hung, Yen-Cheng Wen, Kyle Gallivan, Resve A. Saleh: Improving the performance of parallel relaxation-based circuit simulators. IEEE Trans. on CAD of Integrated Circuits and Systems 12(11): 1762-1774 (1993)
1992
12	EE	Ken Kubiak, Steven Parkes, W. Kent Fuchs, Resve A. Saleh: Exact Evaluation of Diagnostic Test Resolution. DAC 1992: 347-352
11	EE	Yun-Cheng Ju, Resve A. Saleh: Incremental Circuit Simulation Using Waveform Relaxation. DAC 1992: 8-11
10	EE	Eugene Z. Xia, Resve A. Saleh: Parallel waveform-Newton algorithms for circuit simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 11(4): 432-442 (1992)
1991
9	EE	Yun-Cheng Ju, Resve A. Saleh: Incremental Techniques for the Identification of Statically Sensitizable Critical Paths. DAC 1991: 541-546
8		Jaidip Singh, Resve A. Saleh: iMACSIM: A Program for Multi-Level Analog Circuit Simulation. ICCAD 1991: 16-19
7		Yen-Cheng Wen, Kyle Gallivan, Resve A. Saleh: Parallel Event-Driven Waveform Relaxation. ICCD 1991: 101-104
6		Yun-Cheng Ju, Resve A. Saleh: Identification of Viable Paths Using Binary Decision Diagrams. ICCD 1991: 638-641
5	EE	Yun-Cheng Ju, Vasant B. Rao, Resve A. Saleh: Consistency checking and optimization of macromodels. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 957-967 (1991)
1990
4	EE	Gih-Guang Hung, Yen-Cheng Wen, Kyle Gallivan, Resve A. Saleh: Parallel Circuit Simulation Using Hierarchical Relaxation. DAC 1990: 394-399
3		Yun-Cheng Ju, Fred L. Yang, Resve A. Saleh: Mixed-Mode Incremental Simulation and Concurrent Fault Simulation. ICCAD 1990: 158-161
2	EE	Resve A. Saleh, Jacob K. White: Accelerating relaxation algorithms for circuit simulation using waveform-Newton and step-size refinement. IEEE Trans. on CAD of Integrated Circuits and Systems 9(9): 951-958 (1990)
1989
1	EE	Resve A. Saleh, A. Richard Newton: The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 8(12): 1286-1298 (1989)

Coauthor Index

1	Uthman Alsaiari	[37] [45] [55]
2	Lorena Anghel	[49]
3	Brian A. A. Antao	[15] [16]
4	Karim Arabi	[36] [44] [48] [52]
5	Alireza Nasiri Avanaki	[41]
6	Pallab K. Chatterjee	[46]
7	Robbert Dobkins	[46]
8	Zahra Sadat Ebadi	[41] [57]
9	W. Kent Fuchs	[12]
10	Masahiro Fukui	[58]
11	Kyle A. Gallivan (Kyle Gallivan)	[4] [7] [13] [14]
12	Cristian Grecu	[21] [24] [25] [26] [27] [29] [31] [32] [33] [39] [40] [42] [49]
13	Peter Hallschmid	[34] [50] [51]
14	Mama Hamour	[22]
15	Gih-Guang Hung	[4] [13]
16	Syed Zakir Hussain	[18]
17	André Ivanov	[19] [21] [22] [24] [25] [26] [27] [29] [31] [32] [33] [39] [40] [41] [42] [49]
18	Michael Jones	[27] [31]
19	Yun-Cheng Ju	[3] [5] [6] [9] [11]
20	T. Kadowaki	[20]
21	Amit Kedia	[47]
22	Tatsuya Koyagi	[58]
23	Ken Kubiak	[12]
24	G. Lim	[20]
25	Sohaib Majzoub	[61]
26	Xiongfei Meng	[36] [44] [48] [52] [62]
27	Giovanni De Micheli	[29]
28	Shahriar Mirabbasi	[22] [23] [38]
29	Reza Molavi	[38]
30	J. G. Mueller	[15]
31	Jeff Mueller	[53] [56]
32	Mohsen Nahvi	[19]
33	A. Richard Newton	[1]
34	Victor Aken Ova	[35]
35	David Overhauser	[17] [18]
36	Partha Pratim Pande	[21] [24] [25] [26] [27] [29] [31] [32] [33] [39] [40] [42] [49]
37	Steven Parkes	[12]
38	Ivan Pesic	[46]
39	Vasant B. Rao	[5]
40	Steffen Rochel	[18]
41	Joseph Sawicki	[46]
42	Dipanjan Sengupta	[30] [43] [54] [59] [60]
43	S. Shang	[23]
44	Jaidip Singh	[8] [16]
45	Mike Smayling	[46]
46	Egor S. Sogomonyan	[39]
47	Sandy Taylor	[17]
48	K. Uchiyama	[20]
49	Baosheng Wang	[32]
50	Rabab Ward	[61]
51	Yen-Cheng Wen	[4] [7] [13] [14]
52	Jacob K. White (Jacob White)	[2]
53	Eugene Z. Xia	[10]
54	Fred L. Yang	[3]

Colors in the list of coauthors