L. Garcia-Deiros

List of publications from the DBLP Bibliography Server - FAQ

2007

1 EE Salvador Manich, L. Garcia-Deiros, Joan Figueras: Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2046-2058 (2007)

2007
1	EE	Salvador Manich, L. Garcia-Deiros, Joan Figueras: Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2046-2058 (2007)

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