2007 |
16 | EE | Yu-Tsao Hsing,
Chun-Chieh Huang,
Jen-Chieh Yeh,
Cheng-Wen Wu:
SDRAM Delay Fault Modeling and Performance Testing.
VTS 2007: 53-58 |
15 | EE | Rei-Fu Huang,
Jin-Fu Li,
Jen-Chieh Yeh,
Cheng-Wen Wu:
Raisin: Redundancy Analysis Algorithm Simulation.
IEEE Design & Test of Computers 24(4): 386-396 (2007) |
14 | EE | Jen-Chieh Yeh,
Kuo-Liang Cheng,
Yung-Fa Chou,
Cheng-Wen Wu:
Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1101-1113 (2007) |
2006 |
13 | EE | Chen-Hsing Wang,
Chih-Yen Lo,
Min-Sheng Lee,
Jen-Chieh Yeh,
Chih-Tsun Huang,
Cheng-Wen Wu,
Shi-Yu Huang:
A network security processor design based on an integrated SOC design and test platform.
DAC 2006: 490-495 |
12 | EE | Mu-Hsien Hsu,
Yu-Tsao Hsing,
Jen-Chieh Yeh,
Cheng-Wen Wu:
Fault-Pattern Oriented Defect Diagnosis for Flash Memory.
MTDT 2006: 3-8 |
2005 |
11 | EE | Yu-Chun Dawn,
Jen-Chieh Yeh,
Cheng-Wen Wu,
Chia-Ching Wang,
Yung-Chen Lin,
Chao-Hsun Chen:
Flash Memory Die Sort by a Sample Classification Method.
Asian Test Symposium 2005: 182-187 |
10 | EE | Jen-Chieh Yeh,
Yan-Ting Lai,
Yuan-Yuan Shih,
Cheng-Wen Wu,
Chien-Hung Ho,
Yen-Tai Lin:
Flash Memory Built-In Self-Diagnosis with Test Mode Control.
VTS 2005: 15-20 |
9 | EE | Jin-Fu Li,
Jen-Chieh Yeh,
Rei-Fu Huang,
Cheng-Wen Wu:
A built-in self-repair design for RAMs with 2-D redundancy.
IEEE Trans. VLSI Syst. 13(6): 742-745 (2005) |
2004 |
8 | EE | Chih-Tsun Huang,
Jen-Chieh Yeh,
Yuan-Yuan Shih,
Rei-Fu Huang,
Cheng-Wen Wu:
On Test and Diagnostics of Flash Memories.
Asian Test Symposium 2004: 260-265 |
2003 |
7 | EE | Jin-Fu Li,
Jen-Chieh Yeh,
Rei-Fu Huang,
Cheng-Wen Wu,
Peir-Yuan Tsai,
Archer Hsu,
Eugene Chow:
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy.
ITC 2003: 393-402 |
2002 |
6 | EE | Jen-Chieh Yeh,
Chi-Feng Wu,
Kuo-Liang Cheng,
Yung-Fa Chou,
Chih-Tsun Huang,
Cheng-Wen Wu:
Flash Memory Built-In Self-Test Using March-Like Algorithm.
DELTA 2002: 137-141 |
5 | EE | Rei-Fu Huang,
Jin-Fu Li,
Jen-Chieh Yeh,
Cheng-Wen Wu:
A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories.
IOLTW 2002: 262- |
4 | EE | Sau-Kwo Chiu,
Jen-Chieh Yeh,
Chih-Tsun Huang,
Cheng-Wen Wu:
Diagonal Test and Diagnostic Schemes for Flash Memorie.
ITC 2002: 37-46 |
3 | EE | Rei-Fu Huang,
Jin-Fu Li,
Jen-Chieh Yeh,
Cheng-Wen Wu:
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories.
MTDT 2002: 68- |
2 | EE | Kuo-Liang Cheng,
Jen-Chieh Yeh,
Chih-Wea Wang,
Chih-Tsun Huang,
Cheng-Wen Wu:
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics.
VTS 2002: 281-288 |
2001 |
1 | EE | Kuo-Liang Cheng,
Chia-Ming Hsueh,
Jing-Reng Huang,
Jen-Chieh Yeh,
Chih-Tsun Huang,
Cheng-Wen Wu:
Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip.
Asian Test Symposium 2001: 91-96 |