| 2009 |
|---|
| 73 | EE | Tai-Ying Jiang,
Chien-Nan Jimmy Liu,
Jing-Yang Jou:
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 272-284 (2009) |
| 2007 |
|---|
| 72 | EE | Bu-Ching Lin,
Geeng-Wei Lee,
Juinn-Dar Huang,
Jing-Yang Jou:
A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses.
ASP-DAC 2007: 165-170 |
| 71 | EE | Cheng-Yeh Wang,
Chih-Bin Kuo,
Jing-Yang Jou:
Hybrid Wordlength Optimization Methods of Pipelined FFT Processors.
IEEE Trans. Computers 56(8): 1105-1118 (2007) |
| 70 | EE | Tai-Ying Jiang,
Chien-Nan Jimmy Liu,
Jing-Yang Jou:
Observability Analysis on HDL Descriptions for Effective Functional Validation.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1509-1521 (2007) |
| 69 | EE | Chih-Yang Hsu,
Wen-Tsan Hsieh,
Chien-Nan Jimmy Liu,
Jing-Yang Jou:
A Tableless Approach for High-Level Power Modeling Using Neural Networks.
J. Inf. Sci. Eng. 23(1): 71-90 (2007) |
| 2006 |
|---|
| 68 | EE | Man-Yun Su,
Che-Hua Shih,
Juinn-Dar Huang,
Jing-Yang Jou:
FSM-based transaction-level functional coverage for interface compliance verification.
ASP-DAC 2006: 448-453 |
| 67 | EE | Chien-Hua Chen,
Geeng-Wei Lee,
Juinn-Dar Huang,
Jing-Yang Jou:
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication.
ASP-DAC 2006: 600-605 |
| 66 | EE | Iris Hui-Ru Jiang,
Song-Ra Pan,
Yao-Wen Chang,
Jing-Yang Jou:
Reliable crosstalk-driven interconnect optimization.
ACM Trans. Design Autom. Electr. Syst. 11(1): 88-103 (2006) |
| 65 | EE | Chia-Chih Yen,
Jing-Yang Jou:
An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging.
IEEE Trans. Computers 55(11): 1356-1366 (2006) |
| 2005 |
|---|
| 64 | EE | Tai-Ying Jiang,
Chien-Nan Jimmy Liu,
Jing-Yang Jou:
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness.
ASP-DAC 2005: 323-326 |
| 63 | EE | Liang-Yu Lin,
Cheng-Yeh Wang,
Pao-Jui Huang,
Chih-Chieh Chou,
Jing-Yang Jou:
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip.
ASP-DAC 2005: 39-44 |
| 62 | EE | Shang-Wei Tu,
Jing-Yang Jou,
Yao-Wen Chang:
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction.
ISCAS (4) 2005: 4134-4137 |
| 61 | EE | Hsu-Wei Huang,
Cheng-Yeh Wang,
Jing-Yang Jou:
An efficient heterogeneous tree multiplexer synthesis technique.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1622-1629 (2005) |
| 2004 |
|---|
| 60 | EE | Shang-Wei Tu,
Jing-Yang Jou,
Yao-Wen Chang:
Layout techniques for on-chip interconnect inductance reduction.
ASP-DAC 2004: 269-273 |
| 59 | EE | Hsu-Wei Huang,
Cheng-Yeh Wang,
Jing-Yang Jou:
Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming.
ASP-DAC 2004: 280-283 |
| 58 | EE | Hue-Min Lin,
Chia-Chih Yen,
Che-Hua Shih,
Jing-Yang Jou:
On compliance test of on-chip bus for SOC.
ASP-DAC 2004: 328-333 |
| 57 | EE | Chen-Ling Chou,
Chun-Yao Wang,
Geeng-Wei Lee,
Jing-Yang Jou:
Graph Automorphism-Based Algorithm for Determining Symmetric Inputs.
ICCD 2004: 417-419 |
| 56 | | Shang-Wei Tu,
Jing-Yang Jou,
Yao-Wen Chang:
RLC effects on worst-case switching pattern for on-chip buses.
ISCAS (2) 2004: 945-948 |
| 55 | | Yi-Wei Lin,
Jing-Yang Jou:
An efficient approach for hierarchical submodule extraction.
ISCAS (5) 2004: 237-240 |
| 54 | | Lily Huang,
Tai-Ying Jiang,
Jing-Yang Jou,
Heng-Liang Huang:
An efficient logic extraction algorithm using partitioning and circuit encoding.
ISCAS (5) 2004: 249-252 |
| 53 | EE | Geeng-Wei Lee,
Juinn-Dar Huang,
Jing-Yang Jou,
Chun-Yao Wang:
Verification on Port Connections.
ITC 2004: 830-836 |
| 52 | EE | Chia-Chih Yen,
Jing-Yang Jou,
Kuang-Chien Chen:
A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation.
IEEE Design & Test of Computers 21(2): 111-120 (2004) |
| 51 | EE | Iris Hui-Ru Jiang,
Yao-Wen Chang,
Jing-Yang Jou,
Kai-Yuan Chao:
Simultaneous floor plan and buffer-block optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 694-703 (2004) |
| 2003 |
|---|
| 50 | EE | Che-Hua Shih,
Jing-Yang Jou:
An efficient approach for error diagnosis in HDL design.
ISCAS (4) 2003: 732-735 |
| 49 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
SoC design integration by using automatic interconnection rectification.
ISCAS (4) 2003: 744-747 |
| 48 | EE | Chien-Nan Jimmy Liu,
I-Ling Chen,
Jing-Yang Jou:
A Design-for-Verification Technique for Functional Pattern Reduction.
IEEE Design & Test of Computers 20(2): 48-55 (2003) |
| 47 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
Automatic interconnection rectification for SoC design verification based on the port order fault model.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 104-114 (2003) |
| 2002 |
|---|
| 46 | EE | Tai-Ying Jiang,
Chien-Nan Jimmy Liu,
Jing-Yang Jou:
Effective Error Diagnosis for RTL Designs in HDLs.
Asian Test Symposium 2002: 362-367 |
| 45 | | Chia-Chih Yen,
Kuang-Chien Chen,
Jing-Yang Jou:
A Practical Approach to Cycle Bound Estimation for Property Checking.
IWLS 2002: 149-154 |
| 44 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1225-1232 (2002) |
| 43 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
On automatic-verification pattern generation for SoC withport-order fault model.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 466-479 (2002) |
| 42 | EE | Heng-Liang Huang,
Jing-Yang Jou:
Bootstrap Monte Carlo with Adaptive Stratification for Power Estimation.
Journal of Circuits, Systems, and Computers 11(4): 333-350 (2002) |
| 2001 |
|---|
| 41 | EE | Chien-Nan Jimmy Liu,
I-Ling Chen,
Jing-Yang Jou:
An efficient design-for-verification technique for HDLs.
ASP-DAC 2001: 103-108 |
| 40 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model.
Asian Test Symposium 2001: 431-436 |
| 39 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
An AVPG for SOC design verification with port order fault model.
ISCAS (5) 2001: 259-262 |
| 38 | EE | Hen-Ming Lin,
Jing-Yang Jou:
On tri-state buffer inference in HDL synthesis.
ISCAS (5) 2001: 45-48 |
| 37 | EE | Heng-Liang Huang,
Yeong-Ren Chen,
Jing-Yang Jou,
Wen-Zen Shen:
Grouped input power sensitive transition an input sequence compaction technique for power estimation.
ISCAS (5) 2001: 471-474 |
| 36 | EE | Chien-Nan Jimmy Liu,
Chia-Chih Yen,
Jing-Yang Jou:
Automatic Functional Vector Generation Using the Interacting FSM Model.
ISQED 2001: 372-377 |
| 35 | EE | Jie-Hong Roland Jiang,
Jing-Yang Jou,
Juinn-Dar Huang:
Unified functional decomposition via encoding for FPGA technology mapping.
IEEE Trans. VLSI Syst. 9(2): 251-260 (2001) |
| 34 | EE | Yi-Jong Yeh,
Sy-Yen Kuo,
Jing-Yang Jou:
Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 172-176 (2001) |
| 2000 |
|---|
| 33 | EE | Heng-Liang Huang,
Jiing-Yuan Lin,
Wen-Zen Shen,
Jing-Yang Jou:
A new method for constructing IP level power model based on power sensitivity.
ASP-DAC 2000: 135-140 |
| 32 | EE | Kwang-Ting Cheng,
Vishwani D. Agrawal,
Jing-Yang Jou,
Li-C. Wang,
Chi-Feng Wu,
Shianling Wu:
Collaboration between Industry and Academia in Test Research.
Asian Test Symposium 2000: 17- |
| 31 | EE | Iris Hui-Ru Jiang,
Song-Ra Pan,
Yao-Wen Chang,
Jing-Yang Jou:
Optimal reliable crosstalk-driven interconnect optimization.
ISPD 2000: 128-133 |
| 30 | EE | Chien-Nan Jimmy Liu,
Jing-Yang Jou:
An Automatic Controller Extractor for HDL Descriptions at the RTL.
IEEE Design & Test of Computers 17(3): 72-77 (2000) |
| 29 | EE | Juinn-Dar Huang,
Jing-Yang Jou,
Wen-Zen Shen:
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping.
IEEE Trans. VLSI Syst. 8(4): 392-400 (2000) |
| 28 | EE | Hen-Ming Lin,
Jing-Yang Jou:
On computing the minimum feedback vertex set of a directed graph bycontraction operations.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 295-307 (2000) |
| 27 | EE | Iris Hui-Ru Jiang,
Yao-Wen Chang,
Jing-Yang Jou:
Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 999-1010 (2000) |
| 1999 |
|---|
| 26 | EE | Jiann-Horng Lin,
Jing-Yang Jou,
Iris Hui-Ru Jiang:
Hierarchical Floorplan Design on the Internet.
ASP-DAC 1999: 189-192 |
| 25 | EE | Iris Hui-Ru Jiang,
Jing-Yang Jou,
Yao-Wen Chang:
Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation.
DAC 1999: 90-95 |
| 24 | EE | Chien-Nan Jimmy Liu,
Jing-Yang Jou:
An Efficient Functional Coverage Test for HDL Descriptions at RTL.
ICCD 1999: 325-327 |
| 23 | EE | Hen-Ming Lin,
Jing-Yang Jou:
Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD.
ICCD 1999: 364- |
| 22 | EE | Jyh-Mou Tseng,
Jing-Yang Jou:
Two-level logic minimization for low power.
ACM Trans. Design Autom. Electr. Syst. 4(1): 52-69 (1999) |
| 21 | EE | Jiing-Yuan Lin,
Wen-Zen Shen,
Jing-Yang Jou:
A structure-oriented power modeling technique for macrocells.
IEEE Trans. VLSI Syst. 7(3): 380-391 (1999) |
| 1998 |
|---|
| 20 | EE | Shing-Wu Tung,
Jing-Yang Jou:
Verification Pattern Generation for Core-Based Design Using Port Order Fault Model.
Asian Test Symposium 1998: 402-407 |
| 19 | EE | Jie-Hong Roland Jiang,
Jing-Yang Jou,
Juinn-Dar Huang:
Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis.
DAC 1998: 712-717 |
| 18 | EE | Juinn-Dar Huang,
Jing-Yang Jou,
Wen-Zen Shen,
Hsien-Ho Chuang:
On circuit clustering for area/delay tradeoff under capacity and pin constraints.
IEEE Trans. VLSI Syst. 6(4): 634-642 (1998) |
| 17 | EE | Shing-Wu Tung,
Jing-Yang Jou:
A Logical Fault Model for Library Coherence Checking.
J. Inf. Sci. Eng. 14(3): 567-586 (1998) |
| 1997 |
|---|
| 16 | EE | Jiing-Yuan Lin,
Wen-Zen Shen,
Jing-Yang Jou:
A power modeling and characterization method for macrocells using structure information.
ICCAD 1997: 502-506 |
| 15 | | Jing-Yang Jou,
Ming-Chang Nien:
Power Driven Partial Scan.
ICCD 1997: 642-647 |
| 14 | EE | Li-Ren Huang,
Jing-Yang Jou,
Sy-Yen Kuo:
Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 1015-1024 (1997) |
| 1996 |
|---|
| 13 | EE | Li-Ren Huang,
Jing-Yang Jou,
Sy-Yen Kuo,
Wen-Bin Liao:
Easily Testable Data Path Allocation Using Input/Output Registers.
Asian Test Symposium 1996: 142- |
| 12 | EE | Li-Ren Huang,
Jing-Yang Jou,
Sy-Yen Kuo:
An Efficient PRPG Strategy By Utilizing Essential Faults.
Asian Test Symposium 1996: 199-204 |
| 11 | EE | Juinn-Dar Huang,
Jing-Yang Jou,
Wen-Zen Shen:
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping.
ICCAD 1996: 13-17 |
| 10 | EE | Jiing-Yuan Lin,
Wen-Zen Shen,
Jing-Yang Jou:
A power modeling and characterization method for the CMOS standard cell library.
ICCAD 1996: 400-404 |
| 1995 |
|---|
| 9 | EE | Jing-Yang Jou:
An effective BIST design for PLA.
Asian Test Symposium 1995: 286-292 |
| 8 | EE | Juinn-Dar Huang,
Jing-Yang Jou,
Wen-Zen Shen:
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture.
ICCAD 1995: 359-363 |
| 7 | EE | Jing-Yang Jou,
Kwang-Ting (Tim) Cheng:
Timing-Driven Partial Scan.
IEEE Design & Test of Computers 12(4): 52-59 (1995) |
| 1992 |
|---|
| 6 | EE | Kwang-Ting Cheng,
Jing-Yang Jou:
A functional fault model for sequential machines.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1065-1073 (1992) |
| 1991 |
|---|
| 5 | | Jing-Yang Jou,
Kwang-Ting Cheng:
Timing-Driven Partial Scan.
ICCAD 1991: 404-407 |
| 1990 |
|---|
| 4 | | Kwang-Ting Cheng,
Jing-Yang Jou:
A Single-State-Transition Fault Model for Sequential Machines.
ICCAD 1990: 226-229 |
| 1988 |
|---|
| 3 | EE | Ruey-Sing Wei,
Steven G. Rothweiler,
Jing-Yang Jou:
BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping.
DAC 1988: 409-414 |
| 2 | | Jing-Yang Jou,
Jacob A. Abraham:
Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing.
ICPP (1) 1988: 359-362 |
| 1 | | Jing-Yang Jou,
Jacob A. Abraham:
Fault-Tolerant FFT Networks.
IEEE Trans. Computers 37(5): 548-561 (1988) |
