| 2008 |
|---|
| 5 | EE | Baker Mohammad,
Martin Saint-Laurent,
Paul Bassett,
Jacob A. Abraham:
Cache Design for Low Power and High Yield.
ISQED 2008: 103-107 |
| 2007 |
|---|
| 4 | EE | Martin Saint-Laurent,
Baker Mohammad,
Paul Bassett:
A 65-nm pulsed latch with a single clocked transistor.
ISLPED 2007: 347-350 |
| 3 | EE | Martin Saint-Laurent:
A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 834-844 (2007) |
| 2002 |
|---|
| 2 | EE | Martin Saint-Laurent,
Vojin G. Oklobdzija,
Simon S. Singh,
Madhavan Swaminathan:
Optimal Sequencing Energy Allocation for CMOS Integrated Systems.
ISQED 2002: 194-199 |
| 2001 |
|---|
| 1 | | Martin Saint-Laurent,
Madhavan Swaminathan,
James D. Meindl:
On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs.
ICCD 2001: 214-220 |
