| 2007 |
|---|
| 9 | EE | Chao-Yang Yeh,
Malgorzata Marek-Sadowska:
Timing-Aware Power-Noise Reduction in Placement.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 527-541 (2007) |
| 2006 |
|---|
| 8 | EE | Chao-Yang Yeh,
Gustavo R. Wilke,
Hongyu Chen,
Subodh M. Reddy,
Hoa-van Nguyen,
Takashi Miyoshi,
William W. Walker,
Rajeev Murgai:
Clock Distribution Architectures: A Comparative Study.
ISQED 2006: 85-91 |
| 2005 |
|---|
| 7 | EE | Chao-Yang Yeh,
Malgorzata Marek-Sadowska:
Skew-programmable clock design for FPGA and skew-aware placement.
FPGA 2005: 33-40 |
| 6 | | Chao-Yang Yeh,
Malgorzata Marek-Sadowska:
Timing-aware power noise reduction in layout.
ICCAD 2005: 627-634 |
| 5 | | Hongyu Chen,
Chao-Yang Yeh,
Gustavo R. Wilke,
Subodh M. Reddy,
Hoa-van Nguyen,
William W. Walker,
Rajeev Murgai:
A sliding window scheme for accurate clock mesh analysis.
ICCAD 2005: 939-946 |
| 2004 |
|---|
| 4 | EE | Chao-Yang Yeh,
Malgorzata Marek-Sadowska:
Sequential delay budgeting with interconnect prediction.
IEEE Trans. VLSI Syst. 12(10): 1028-1037 (2004) |
| 2003 |
|---|
| 3 | EE | Chao-Yang Yeh,
Malgorzata Marek-Sadowska:
Delay budgeting in sequential circuit with application on FPGA placement.
DAC 2003: 202-207 |
| 2 | EE | Chao-Yang Yeh,
Malgorzata Marek-Sadowska:
Minimum-Area Sequential Budgeting for FPGA.
ICCAD 2003: 813-817 |
| 1 | EE | Chao-Yang Yeh,
Malgorzata Marek-Sadowska:
Sequential delay budgeting with interconnect prediction.
SLIP 2003: 23-30 |
