2009 | ||
---|---|---|
62 | EE | Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang: Skew-aware polarity assignment in clock tree. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009) |
2008 | ||
61 | EE | Po-Yuan Chen, Che-Yu Liu, TingTing Hwang: Transition-aware decoupling-capacitor allocation in power noise reduction. ICCAD 2008: 426-429 |
60 | EE | Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang: Synthesis of a novel timing-error detection architecture. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
59 | EE | Shih-Liang Chen, Shu-Ming Chang, Wen-Wei Lin, TingTing Hwang: Digital Secure-Communication Using Robust Hyper-Chaotic Systems. I. J. Bifurcation and Chaos 18(11): 3325-3339 (2008) |
2007 | ||
58 | EE | Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang: Skew aware polarity assignment in clock tree. ICCAD 2007: 376-379 |
57 | EE | Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang: A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current. ACM Trans. Design Autom. Electr. Syst. 12(3): (2007) |
56 | EE | Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang, TingTing Hwang: A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2222-2227 (2007) |
55 | EE | Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu: Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 564-573 (2007) |
54 | EE | Yi-Yu Liu, TingTing Hwang: Crosstalk-Aware Domino-Logic Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1155-1161 (2007) |
53 | EE | Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei Kuan Shih, TingTing Hwang: Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains. The Journal of Supercomputing 42(2): 201-223 (2007) |
2006 | ||
52 | EE | Yu-Hui Huang, Po-Yuan Chen, TingTing Hwang: Switching-activity driven gate sizing and Vth assignment for low power design. ASP-DAC 2006: 576-581 |
51 | EE | Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang: A bus architecture for crosstalk elimination in high performance processor design. CODES+ISSS 2006: 247-252 |
50 | EE | Yi-Yu Liu, TingTing Hwang: Crosstalk-aware domino logic synthesis. DATE 2006: 1312-1317 |
49 | EE | Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu: Performance-driven crosstalk elimination at post-compiler level. ISCAS 2006 |
48 | EE | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu: Decomposition of instruction decoders for low-power designs. ACM Trans. Design Autom. Electr. Syst. 11(4): 880-889 (2006) |
47 | EE | Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang: Crosstalk minimization in logic synthesis for PLAs. ACM Trans. Design Autom. Electr. Syst. 11(4): 890-915 (2006) |
46 | EE | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu: A power-driven multiplication instruction-set design method for ASIPs. IEEE Trans. VLSI Syst. 14(1): 81-85 (2006) |
45 | EE | Chi Ta Wu, Ang-Chih Hsieh, TingTing Hwang: Instruction buffering for nested loops in low-power design. IEEE Trans. VLSI Syst. 14(7): 780-784 (2006) |
2005 | ||
44 | EE | Yi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu: Low-power techniques for network security processors. ASP-DAC 2005: 355-360 |
43 | EE | Tsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu: Functionality directed clustering for low power MTCMOS design. ASP-DAC 2005: 862-867 |
42 | EE | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu: A power-driven multiplication instruction-set design method for ASIPs. ISCAS (4) 2005: 3311-3314 |
2004 | ||
41 | EE | Yen-Te Ho, TingTing Hwang: Low power design using dual threshold voltage. ASP-DAC 2004: 205-208 |
40 | EE | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu: Decomposition of Instruction Decoder for Low Power Design. DATE 2004: 664-665 |
39 | EE | Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang: Crosstalk Minimization in Logic Synthesis for PLA. DATE 2004: 790-795 |
38 | Chi-Wei Hu, TingTing Hwang: Output-pattern directed decomposition for low power design. ISCAS (5) 2004: 137-140 | |
37 | EE | Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei Kuan Shih, TingTing Hwang: Power-Aware Scheduling for Parallel Security Processors with Analytical Models. LCPC 2004: 470-484 |
2003 | ||
36 | EE | Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang: A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. DATE 2003: 11102-11103 |
35 | EE | Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang: G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. DATE 2003: 11134-11135 |
34 | EE | MingHung Lee, TingTing Hwang, Shi-Yu Huang: Decomposition of Extended Finite State Machine for Low Power Design. DATE 2003: 11152-11153 |
33 | EE | Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai: Compiler optimization on VLIW instruction scheduling for low power. ACM Trans. Design Autom. Electr. Syst. 8(2): 252-268 (2003) |
2002 | ||
32 | EE | Chi Ta Wu, TingTing Hwang: Instruction buffering for nested loops in low power design. ISCAS (4) 2002: 81-84 |
31 | EE | Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu: Logic transformation for low-power synthesis. ACM Trans. Design Autom. Electr. Syst. 7(2): 265-283 (2002) |
2001 | ||
30 | EE | LiYi Lin, Yi-Yu Liu, TingTing Hwang: A construction of minimal delay Steiner tree using two-pole delay model. ASP-DAC 2001: 126-132 |
29 | EE | Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu: Binary decision diagram with minimum expected path length. DATE 2001: 708-712 |
28 | EE | Chau-Shen Chen, TingTing Hwang, C. L. Liu: Architecture driven circuit partitioning. IEEE Trans. VLSI Syst. 9(2): 383-389 (2001) |
2000 | ||
27 | EE | Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai: Compiler Optimization on Instruction Scheduling for Low Power. ISSS 2000: 55-61 |
1999 | ||
26 | EE | Shiuann-Shiuh Lin, Wen-Hsin Chen, Wen-Wei Lin, TingTing Hwang: A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning. ASP-DAC 1999: 77-80 |
25 | EE | Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu: Logic Transformation for Low Power Synthesis. DATE 1999: 158-162 |
24 | EE | How-Rern Lin, TingTing Hwang: On determining sensitization criterion in an iterative gate sizing process. IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 231-238 (1999) |
1998 | ||
23 | EE | Jan-Min Hwang, Feng-Yi Chiang, TingTing Hwang: A Re-engineering Approach to Low Power FPGA Design Using SPFD. DAC 1998: 722-725 |
22 | EE | Chau-Shen Chen, TingTing Hwang, C. L. Liu: Architecture driven circuit partitioning. ICCAD 1998: 408-411 |
21 | EE | Chau-Shen Chen, TingTing Hwang: Layout Driven Selection and Chaining of Partial Scan Flip-Flops. J. Electronic Testing 13(1): 19-27 (1998) |
1997 | ||
20 | EE | Chau-Shen Chen, TingTing Hwang, C. L. Liu: Low Power FPGA Design - A Re-engineering Approach. DAC 1997: 656-661 |
19 | EE | Kuo-Hua Wang, TingTing Hwang: Boolean matching for incompletely specified functions. IEEE Trans. on CAD of Integrated Circuits and Systems 16(2): 160-168 (1997) |
18 | EE | Shiuann-Shiuh Lin, Yuh-Ju Lin, TingTing Hwang: Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 316-320 (1997) |
1996 | ||
17 | EE | Chau-Shen Chen, Kuang-Hui Lin, TingTing Hwang: Layout Driven Selecting and Chaining of Partial Scan. DAC 1996: 262-267 |
16 | EE | Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu: Low power realization of finite state machines - a decomposition approach. ACM Trans. Design Autom. Electr. Syst. 1(3): 315-340 (1996) |
15 | EE | Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang: Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1226-1236 (1996) |
14 | EE | Kuo-Hua Wang, TingTing Hwang, Cheng Chen: Exploiting communication complexity for Boolean matching. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1249-1256 (1996) |
1995 | ||
13 | EE | How-Rern Lin, TingTing Hwang: Power recduction by gate sizing with path-oriented slack calculation. ASP-DAC 1995 |
12 | EE | Kuo-Hua Wang, TingTing Hwang: Boolean Matching for Incompletely Specified Functions. DAC 1995: 48-53 |
11 | EE | Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1076-1084 (1995) |
1994 | ||
10 | How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang: Cell Height Driven Transistor Sizing in a Cell Based Module Design. EDAC-ETC-EUROASIC 1994: 425-429 | |
9 | EE | How-Rern Lin, TingTing Hwang: Dynamical identification of critical paths for iterative gate sizing. ICCAD 1994: 481-484 |
8 | Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: State Assignment for Power and Area Minimization. ICCD 1994: 250-254 | |
7 | EE | TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang: Logic synthesis for field-programmable gate arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 13(10): 1280-1287 (1994) |
6 | EE | Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin: Performance-driven interconnection optimization for microarchitecture synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 137-149 (1994) |
1993 | ||
5 | EE | Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: Combining technology mapping and placement for delay-optimization in FPGA designs. ICCAD 1993: 123-127 |
1992 | ||
4 | Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin, TingTing Hwang: ELM-A Fast Addition Algorithm Discovered by a Program. IEEE Trans. Computers 41(9): 1181-1184 (1992) | |
3 | EE | TingTing Hwang, Robert Michael Owens, Mary Jane Irwin: Efficiently computing communication complexity for multilevel logic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 545-554 (1992) |
1990 | ||
2 | EE | TingTing Hwang, Robert Michael Owens, Mary Jane Irwin: Exploiting communication complexity for multilevel logic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 9(10): 1017-1027 (1990) |
1989 | ||
1 | EE | TingTing Hwang, Robert Michael Owens, Mary Jane Irwin: Multi-Level Logic Synthesis Using Communication Complexity. DAC 1989: 215-220 |