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TingTing Hwang

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2009
62EEPo-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang: Skew-aware polarity assignment in clock tree. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009)
2008
61EEPo-Yuan Chen, Che-Yu Liu, TingTing Hwang: Transition-aware decoupling-capacitor allocation in power noise reduction. ICCAD 2008: 426-429
60EEYu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang: Synthesis of a novel timing-error detection architecture. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008)
59EEShih-Liang Chen, Shu-Ming Chang, Wen-Wei Lin, TingTing Hwang: Digital Secure-Communication Using Robust Hyper-Chaotic Systems. I. J. Bifurcation and Chaos 18(11): 3325-3339 (2008)
2007
58EEPo-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang: Skew aware polarity assignment in clock tree. ICCAD 2007: 376-379
57EEAng-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang: A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current. ACM Trans. Design Autom. Electr. Syst. 12(3): (2007)
56EEWen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang, TingTing Hwang: A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2222-2227 (2007)
55EEWu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu: Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 564-573 (2007)
54EEYi-Yu Liu, TingTing Hwang: Crosstalk-Aware Domino-Logic Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1155-1161 (2007)
53EEYung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei Kuan Shih, TingTing Hwang: Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains. The Journal of Supercomputing 42(2): 201-223 (2007)
2006
52EEYu-Hui Huang, Po-Yuan Chen, TingTing Hwang: Switching-activity driven gate sizing and Vth assignment for low power design. ASP-DAC 2006: 576-581
51EEWen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang: A bus architecture for crosstalk elimination in high performance processor design. CODES+ISSS 2006: 247-252
50EEYi-Yu Liu, TingTing Hwang: Crosstalk-aware domino logic synthesis. DATE 2006: 1312-1317
49EEWu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu: Performance-driven crosstalk elimination at post-compiler level. ISCAS 2006
48EEWu-An Kuo, TingTing Hwang, Allen C.-H. Wu: Decomposition of instruction decoders for low-power designs. ACM Trans. Design Autom. Electr. Syst. 11(4): 880-889 (2006)
47EEYi-Yu Liu, Kuo-Hua Wang, TingTing Hwang: Crosstalk minimization in logic synthesis for PLAs. ACM Trans. Design Autom. Electr. Syst. 11(4): 890-915 (2006)
46EEWu-An Kuo, TingTing Hwang, Allen C.-H. Wu: A power-driven multiplication instruction-set design method for ASIPs. IEEE Trans. VLSI Syst. 14(1): 81-85 (2006)
45EEChi Ta Wu, Ang-Chih Hsieh, TingTing Hwang: Instruction buffering for nested loops in low-power design. IEEE Trans. VLSI Syst. 14(7): 780-784 (2006)
2005
44EEYi-Ping You, Chun-Yen Tseng, Yu-Hui Huang, Po-Chiun Huang, TingTing Hwang, Sheng-Yu Hsu: Low-power techniques for network security processors. ASP-DAC 2005: 355-360
43EETsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu: Functionality directed clustering for low power MTCMOS design. ASP-DAC 2005: 862-867
42EEWu-An Kuo, TingTing Hwang, Allen C.-H. Wu: A power-driven multiplication instruction-set design method for ASIPs. ISCAS (4) 2005: 3311-3314
2004
41EEYen-Te Ho, TingTing Hwang: Low power design using dual threshold voltage. ASP-DAC 2004: 205-208
40EEWu-An Kuo, TingTing Hwang, Allen C.-H. Wu: Decomposition of Instruction Decoder for Low Power Design. DATE 2004: 664-665
39EEYi-Yu Liu, Kuo-Hua Wang, TingTing Hwang: Crosstalk Minimization in Logic Synthesis for PLA. DATE 2004: 790-795
38 Chi-Wei Hu, TingTing Hwang: Output-pattern directed decomposition for low power design. ISCAS (5) 2004: 137-140
37EEYung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei Kuan Shih, TingTing Hwang: Power-Aware Scheduling for Parallel Security Processors with Analytical Models. LCPC 2004: 470-484
2003
36EEJennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang: A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. DATE 2003: 11102-11103
35EEAlex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang: G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. DATE 2003: 11134-11135
34EEMingHung Lee, TingTing Hwang, Shi-Yu Huang: Decomposition of Extended Finite State Machine for Low Power Design. DATE 2003: 11152-11153
33EEChingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai: Compiler optimization on VLIW instruction scheduling for low power. ACM Trans. Design Autom. Electr. Syst. 8(2): 252-268 (2003)
2002
32EEChi Ta Wu, TingTing Hwang: Instruction buffering for nested loops in low power design. ISCAS (4) 2002: 81-84
31EEKi-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu: Logic transformation for low-power synthesis. ACM Trans. Design Autom. Electr. Syst. 7(2): 265-283 (2002)
2001
30EELiYi Lin, Yi-Yu Liu, TingTing Hwang: A construction of minimal delay Steiner tree using two-pole delay model. ASP-DAC 2001: 126-132
29EEYi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu: Binary decision diagram with minimum expected path length. DATE 2001: 708-712
28EEChau-Shen Chen, TingTing Hwang, C. L. Liu: Architecture driven circuit partitioning. IEEE Trans. VLSI Syst. 9(2): 383-389 (2001)
2000
27EEChingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai: Compiler Optimization on Instruction Scheduling for Low Power. ISSS 2000: 55-61
1999
26EEShiuann-Shiuh Lin, Wen-Hsin Chen, Wen-Wei Lin, TingTing Hwang: A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning. ASP-DAC 1999: 77-80
25EEKi-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu: Logic Transformation for Low Power Synthesis. DATE 1999: 158-162
24EEHow-Rern Lin, TingTing Hwang: On determining sensitization criterion in an iterative gate sizing process. IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 231-238 (1999)
1998
23EEJan-Min Hwang, Feng-Yi Chiang, TingTing Hwang: A Re-engineering Approach to Low Power FPGA Design Using SPFD. DAC 1998: 722-725
22EEChau-Shen Chen, TingTing Hwang, C. L. Liu: Architecture driven circuit partitioning. ICCAD 1998: 408-411
21EEChau-Shen Chen, TingTing Hwang: Layout Driven Selection and Chaining of Partial Scan Flip-Flops. J. Electronic Testing 13(1): 19-27 (1998)
1997
20EEChau-Shen Chen, TingTing Hwang, C. L. Liu: Low Power FPGA Design - A Re-engineering Approach. DAC 1997: 656-661
19EEKuo-Hua Wang, TingTing Hwang: Boolean matching for incompletely specified functions. IEEE Trans. on CAD of Integrated Circuits and Systems 16(2): 160-168 (1997)
18EEShiuann-Shiuh Lin, Yuh-Ju Lin, TingTing Hwang: Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 316-320 (1997)
1996
17EEChau-Shen Chen, Kuang-Hui Lin, TingTing Hwang: Layout Driven Selecting and Chaining of Partial Scan. DAC 1996: 262-267
16EESue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu: Low power realization of finite state machines - a decomposition approach. ACM Trans. Design Autom. Electr. Syst. 1(3): 315-340 (1996)
15EEShih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang: Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1226-1236 (1996)
14EEKuo-Hua Wang, TingTing Hwang, Cheng Chen: Exploiting communication complexity for Boolean matching. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1249-1256 (1996)
1995
13EEHow-Rern Lin, TingTing Hwang: Power recduction by gate sizing with path-oriented slack calculation. ASP-DAC 1995
12EEKuo-Hua Wang, TingTing Hwang: Boolean Matching for Incompletely Specified Functions. DAC 1995: 48-53
11EEChau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1076-1084 (1995)
1994
10 How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang: Cell Height Driven Transistor Sizing in a Cell Based Module Design. EDAC-ETC-EUROASIC 1994: 425-429
9EEHow-Rern Lin, TingTing Hwang: Dynamical identification of critical paths for iterative gate sizing. ICCAD 1994: 481-484
8 Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: State Assignment for Power and Area Minimization. ICCD 1994: 250-254
7EETingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang: Logic synthesis for field-programmable gate arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 13(10): 1280-1287 (1994)
6EEYi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin: Performance-driven interconnection optimization for microarchitecture synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 137-149 (1994)
1993
5EEChau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin: Combining technology mapping and placement for delay-optimization in FPGA designs. ICCAD 1993: 123-127
1992
4 Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin, TingTing Hwang: ELM-A Fast Addition Algorithm Discovered by a Program. IEEE Trans. Computers 41(9): 1181-1184 (1992)
3EETingTing Hwang, Robert Michael Owens, Mary Jane Irwin: Efficiently computing communication complexity for multilevel logic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 545-554 (1992)
1990
2EETingTing Hwang, Robert Michael Owens, Mary Jane Irwin: Exploiting communication complexity for multilevel logic synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 9(10): 1017-1027 (1990)
1989
1EETingTing Hwang, Robert Michael Owens, Mary Jane Irwin: Multi-Level Logic Synthesis Using Communication Complexity. DAC 1989: 215-220

Coauthor Index

1Alex C.-Y. Chang [35]
2Po-Hsien Chang [60]
3Shih-Chieh Chang [15] [60]
4Shu-Ming Chang [59]
5Tsuang-Wei Chang [43] [57]
6Chau-Shen Chen [5] [11] [17] [20] [21] [22] [28]
7Cheng Chen [14]
8Po-Yuan Chen [51] [52] [56] [58] [61] [62]
9Shih-Liang Chen [59]
10Wen-Hsin Chen [26]
11Feng-Yi Chiang [23]
12Yi-Ling Chiang [49] [55]
13Ching-Lung Chou [10]
14Sue-Hong Chow [16]
15Kuan-Hsien Ho [58] [62]
16Yen-Te Ho [41]
17Yi-Cheng Ho [16]
18Ang-Chih Hsieh [45] [57]
19Wen-Wen Hsieh [51] [56]
20Sheng-Yu Hsu [43] [44]
21Yu-Chin Hsu [10]
22Chi-Wei Hu [38]
23Chung-Wen Huang [37] [53]
24Po-Chiun Huang [44]
25Shi-Yu Huang [34]
26Yu-Hui Huang [44] [52]
27Jan-Min Hwang [23]
28Mary Jane Irwin [1] [2] [3] [4] [7]
29Yi-Min Jiang [6]
30Sung-Mo Kang [25] [31]
31Thomas P. Kelliher [4]
32Ki-Wook Kim [25] [31]
33Taewhan Kim [31]
34Wu-An Kuo [35] [36] [40] [42] [46] [48] [49] [55]
35Chingren Lee [27] [33]
36Jenq Kuen Lee [27] [33] [37] [53]
37MingHung Lee [34]
38Tsing-Fa Lee [6]
39How-Rern Lin [9] [10] [13] [24]
40Kuang-Hui Lin [17]
41LiYi Lin [30]
42Shiuann-Shiuh Lin [18] [26]
43Tzu-Teng Lin [57]
44Wen-Wei Lin [26] [59]
45Youn-Long Lin [5] [6] [8] [11]
46Yuh-Ju Lin [18]
47Yung-Chia Lin [37] [53]
48C. L. Liu (Chung Laung (Dave) Liu) [16] [20] [22] [25] [28] [29] [31]
49Che-Yu Liu [61]
50Yi-Yu Liu [29] [30] [39] [47] [50] [54]
51Jennifer Y.-L. Lo [36]
52Malgorzata Marek-Sadowska [15]
53Robert Michael Owens [1] [2] [3] [4] [7]
54Wei Kuan Shih [37] [53]
55Yu-Shih Su [60]
56Shi-Chun Tsai [27] [33]
57Yu-Wen Tsay [5] [11]
58Chun-Yen Tseng [44]
59Chun-Yao Wang [56]
60Kuo-Hua Wang [7] [8] [12] [14] [19] [29] [39] [47]
61Wen-Sing Wang [8]
62Allen C.-H. Wu [5] [8] [11] [35] [36] [40] [42] [46] [48] [49] [55]
63Chi Ta Wu [32] [45]
64Yi-Ping You [37] [44] [53]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)