2009 |
25 | EE | Yung-Chih Chen,
Chun-Yao Wang:
Enhancing SAT-based sequential depth computation by pruning search space.
ACM Great Lakes Symposium on VLSI 2009: 397-400 |
24 | EE | Meng-Syue Chan,
Chun-Yao Wang,
Yung-Chih Chen:
An efficient approach to sip design integration.
ISQED 2009: 241-247 |
23 | EE | Yi-Ling Liu,
Chun-Yao Wang,
Yung-Chih Chen,
Ya-Hsin Chang:
A novel ACO-based pattern generation for peak power estimation in VLSI circuits.
ISQED 2009: 317-323 |
2008 |
22 | EE | Chun-Yao Wang,
Daniel J. Buehrer:
A Ring-Based Decentralized Collaborative Non-blocking Atomic Commit Protocol.
IAT 2008: 395-398 |
21 | EE | Chuang-Chi Chiou,
Chun-Yao Wang,
Yung-Chih Chen:
A Statistic-Based Approach to Testability Analysis.
ISQED 2008: 267-270 |
20 | EE | Shih-Chieh Wu,
Chun-Yao Wang,
Yung-Chih Chen:
Novel Probabilistic Combinational Equivalence Checking.
IEEE Trans. VLSI Syst. 16(4): 365-375 (2008) |
19 | EE | Yung-Chih Chen,
Chun-Yao Wang:
An Implicit Approach to Minimizing Range-Equivalent Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 1942-1955 (2008) |
18 | EE | Min-Lun Chuang,
Chun-Yao Wang:
Synthesis of reversible sequential elements.
JETC 3(4): (2008) |
2007 |
17 | EE | Min-Lun Chuang,
Chun-Yao Wang:
Synthesis of Reversible Sequential Elements.
ASP-DAC 2007: 420-425 |
16 | EE | Tsung-Lin Lee,
Chun-Yao Wang:
Recognition of Fanout-free Functions.
ASP-DAC 2007: 426-431 |
15 | EE | Yu-Min Kuo,
Cheng-Hung Lin,
Chun-Yao Wang,
Shih-Chieh Chang,
Pei-Hsin Ho:
Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure.
ISQED 2007: 344-349 |
14 | EE | Wen-Wen Hsieh,
Po-Yuan Chen,
Chun-Yao Wang,
TingTing Hwang:
A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2222-2227 (2007) |
2006 |
13 | EE | Ming-Hong Su,
Chun-Yao Wang:
High level equivalence symmetric input identification.
ASP-DAC 2006: 249-253 |
12 | EE | Yi-Le Huang,
Chun-Yao Wang,
Richard Yeh,
Shih-Chieh Chang,
Yung-Chih Chen:
Language-Based High Level Transaction Extraction on On-chip Buses.
ISQED 2006: 231-236 |
11 | EE | Shih-Chieh Wu,
Chun-Yao Wang:
PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking.
VLSI-SoC 2006: 104-109 |
2005 |
10 | EE | Yung-Chih Chen,
Chun-Yao Wang:
An Improved Approach for AlternativeWires Identi.cation.
ICCD 2005: 711-716 |
2004 |
9 | EE | Chen-Ling Chou,
Chun-Yao Wang,
Geeng-Wei Lee,
Jing-Yang Jou:
Graph Automorphism-Based Algorithm for Determining Symmetric Inputs.
ICCD 2004: 417-419 |
8 | EE | Geeng-Wei Lee,
Juinn-Dar Huang,
Jing-Yang Jou,
Chun-Yao Wang:
Verification on Port Connections.
ITC 2004: 830-836 |
7 | EE | Daniel J. Buehrer,
Chun-Yao Wang:
Using a Class Algebra Ontology To Define Conversions between OWL/SQL/Java Beans.
Web Intelligence 2004: 752-754 |
2003 |
6 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
SoC design integration by using automatic interconnection rectification.
ISCAS (4) 2003: 744-747 |
5 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
Automatic interconnection rectification for SoC design verification based on the port order fault model.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 104-114 (2003) |
2002 |
4 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1225-1232 (2002) |
3 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
On automatic-verification pattern generation for SoC withport-order fault model.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 466-479 (2002) |
2001 |
2 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model.
Asian Test Symposium 2001: 431-436 |
1 | EE | Chun-Yao Wang,
Shing-Wu Tung,
Jing-Yang Jou:
An AVPG for SOC design verification with port order fault model.
ISCAS (5) 2001: 259-262 |