Noel Menezes

2008
25	EE	Noel Menezes, Chandramouli V. Kashyap, Chirayu S. Amin: A "true" electrical cell model for timing, noise, and power grid verification. DAC 2008: 462-467
2007
24	EE	Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James Tschanz, Vivek De: Comparative Analysis of Conventional and Statistical Design Techniques. DAC 2007: 238-243
23	EE	Chandramouli V. Kashyap, Chirayu S. Amin, Noel Menezes, Eli Chiprout: A nonlinear cell macromodel for digital applications. ICCAD 2007: 678-685
22	EE	Noel Menezes: The good, the bad, and the statistical. ISPD 2007: 168
21	EE	Farid N. Najm, Noel Menezes, Imad A. Ferzli: A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 574-591 (2007)
2006
20	EE	Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout: A multi-port current source model for multiple-input switching effects in CMOS library cells. DAC 2006: 247-252
2005
19	EE	Florentin Dartu, Anirudh Devgan, Noel Menezes: Variability modeling and variability-aware design in deep submicron integrated circuits. ACM Great Lakes Symposium on VLSI 2005: 1
18	EE	Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail: Statistical static timing analysis: how simple can we get? DAC 2005: 652-657
2004
17	EE	Farid N. Najm, Noel Menezes: Statistical timing analysis based on a timing yield model. DAC 2004: 460-465
16	EE	Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick: Repeater scaling and its impact on CAD. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 451-463 (2004)
2003
15	EE	Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick: The scaling challenge: can correct-by-construction design help? ISPD 2003: 51-58
2001
14		Noel Menezes, Sachin S. Sapatnekar: Optimization and Analysis Techniques for the Deep Submicron Regime. VLSI Design 2001: 3-4
1999
13	EE	Chung-Ping Chen, Noel Menezes: Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching. DAC 1999: 502-506
12	EE	Noel Menezes, Chung-Ping Chen: Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect. VLSI Design 1999: 476-
1997
11		Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi: Clustering and Load Balancing for Buffered Clock Tree Synthesis. ICCD 1997: 217-223
10	EE	Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi: Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. IEEE Trans. on CAD of Integrated Circuits and Systems 16(2): 210-215 (1997)
9	EE	Noel Menezes, Ross Baldick, Lawrence T. Pileggi: A sequential quadratic programming approach to concurrent gate and wire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 16(8): 867-881 (1997)
1996
8	EE	Florentin Dartu, Noel Menezes, Lawrence T. Pileggi: Performance computation for precharacterized CMOS gates with RC loads. IEEE Trans. on CAD of Integrated Circuits and Systems 15(5): 544-553 (1996)
7	EE	Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi: Post-processing of clock trees via wiresizing and buffering for robust design. IEEE Trans. on CAD of Integrated Circuits and Systems 15(6): 691-701 (1996)
1995
6	EE	Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi: Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. DAC 1995: 690-695
5	EE	Noel Menezes, Ross Baldick, Lawrence T. Pileggi: A sequential quadratic programming approach to concurrent gate and wire sizing. ICCAD 1995: 144-151
1994
4	EE	Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage: A Gate-Delay Model for high-Speed CMOS Circuits. DAC 1994: 576-580
3		Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer: Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. EDAC-ETC-EUROASIC 1994: 332-337
2	EE	Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage: RC interconnect synthesis-a moment fitting approach. ICCAD 1994: 418-425
1993
1	EE	Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage: Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. DAC 1993: 165-170

Coauthor Index

1	Chirayu S. Amin	[18] [20] [23] [25]
2	Ross Baldick	[5] [9]
3	Keith A. Bowman	[24]
4	Ronn B. Brashear	[3]
5	Steven M. Burns	[24]
6	Charlie Chung-Ping Chen (Chung-Ping Chen)	[12] [13]
7	Yao-Ping Chen	[11]
8	Eli Chiprout	[20] [23]
9	Umakanta Choudhury	[18]
10	Pasquale Cocchini	[15] [16]
11	Florentin Dartu	[2] [4] [8] [18] [19]
12	Vivek De	[24]
13	Anirudh Devgan	[19]
14	Imad A. Ferzli	[21]
15	Nagib Hakim	[18]
16	Yehea I. Ismail	[18]
17	Chandramouli V. Kashyap	[20] [23] [25]
18	Mahesh Ketkar	[24]
19	Kip Killpack	[18] [20]
20	Desmond Kirkpatrick	[15] [16]
21	Ashih D. Mehta	[11]
22	M. Ray Mercer	[3]
23	Farid N. Najm	[17] [21]
24	Chanhee Oh	[3]
25	Lawrence T. Pileggi (Larry T. Pileggi, Lawrence T. Pillage)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
26	Satyamurthy Pullela	[1] [2] [6] [7] [10]
27	Jessica Qian	[4]
28	Sachin S. Sapatnekar	[14]
29	Prashant Saxena	[15] [16]
30	James Tschanz	[24]
31	Martin D. F. Wong (D. F. Wong)	[11]