| 2009 |
|---|
| 7 | EE | Rajesh Amratlal Thakker,
Maryam Shojaei Baghini,
Mahesh B. Patil:
Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization.
VLSI Design 2009: 427-432 |
| 2007 |
|---|
| 6 | EE | B. P. Harish,
Navakanta Bhat,
Mahesh B. Patil:
Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs.
ICCTA 2007: 94-98 |
| 5 | EE | B. P. Harish,
Navakanta Bhat,
Mahesh B. Patil:
On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 606-614 (2007) |
| 2006 |
|---|
| 4 | EE | Palkesh Jain,
D. Vinay Kumar,
J. M. Vasi,
Mahesh B. Patil:
Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits.
VLSI Design 2006: 188-193 |
| 2003 |
|---|
| 3 | EE | D. Vinay Kumar,
Nihar R. Mohapatra,
Mahesh B. Patil,
V. Ramgopal Rao:
Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits.
VLSI Design 2003: 128- |
| 1999 |
|---|
| 2 | EE | Mahesh B. Patil:
Extension of the VR discretization scheme for velocity saturation.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1508-1511 (1999) |
| 1998 |
|---|
| 1 | EE | Mahesh B. Patil:
New discretization scheme for two-dimensional semiconductor device simulation on triangular grid.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1160-1165 (1998) |
