| 2009 |
|---|
| 63 | EE | Yulei Zhang,
Ling Zhang,
Alina Deutsch,
George A. Katopis,
Daniel M. Dreps,
James F. Buckwalter,
Ernest S. Kuh,
Chung-Kuan Cheng:
Design methodology of high performance on-chip global interconnect using terminated transmission-line.
ISQED 2009: 451-458 |
| 2008 |
|---|
| 62 | EE | Ling Zhang,
Wenjian Yu,
Haikun Zhu,
Alina Deutsch,
George A. Katopis,
Daniel M. Dreps,
Ernest S. Kuh,
Chung-Kuan Cheng:
Low power passive equalizer optimization using tritonic step response.
DAC 2008: 570-573 |
| 61 | EE | Ling Zhang,
Wenjian Yu,
Yulei Zhang,
Renshen Wang,
Alina Deutsch,
George A. Katopis,
Daniel M. Dreps,
James F. Buckwalter,
Ernest S. Kuh,
Chung-Kuan Cheng:
Low Power Passive Equalizer Design for Computer Memory Links.
Hot Interconnects 2008: 51-56 |
| 60 | EE | Rui Shi,
Wenjian Yu,
Yi Zhu,
Chung-Kuan Cheng,
Ernest S. Kuh:
Efficient and accurate eye diagram prediction for high speed signaling.
ICCAD 2008: 655-661 |
| 2007 |
|---|
| 59 | EE | Zhengyong Zhu,
He Peng,
Chung-Kuan Cheng,
Khosro Rouz,
Manjit Borah,
Ernest S. Kuh:
Two-Stage Newton-Raphson Method for Transistor-Level Simulation.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 881-895 (2007) |
| 2006 |
|---|
| 58 | EE | Zhengyong Zhu,
Rui Shi,
Chung-Kuan Cheng,
Ernest S. Kuh:
An unconditional stable general operator splitting method for transistor level transient analysis.
ASP-DAC 2006: 428-433 |
| 2005 |
|---|
| 57 | EE | Zhengyong Zhu,
Khosro Rouz,
Manjit Borah,
Chung-Kuan Cheng,
Ernest S. Kuh:
Efficient transient simulation for transistor-level analysis.
ASP-DAC 2005: 240-243 |
| 2001 |
|---|
| 56 | EE | Qingjian Yu,
Ernest S. Kuh:
Explicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements.
DATE 2001: 445-450 |
| 55 | EE | Qingjian Yu,
Ernest S. Kuh:
New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees.
ISQED 2001: 151-157 |
| 2000 |
|---|
| 54 | EE | Pinghong Chen,
Ernest S. Kuh:
Floorplan sizing by linear programming approximation.
DAC 2000: 468-471 |
| 53 | EE | Qingjian Yu,
Janet Meiling Wang,
Ernest S. Kuh:
Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks.
DAC 2000: 520-525 |
| 1999 |
|---|
| 52 | EE | Janet Meiling Wang,
Qingjian Yu,
Ernest S. Kuh:
Coupled Noise Estimation for Distributed RC Interconnect Model.
DATE 1999: 664-668 |
| 51 | EE | Janet Meiling Wang,
Ernest S. Kuh,
Qingjian Yu:
The Chebyshev expansion based passive model for distributed interconnect networks.
ICCAD 1999: 370-375 |
| 1998 |
|---|
| 50 | EE | Dongsheng Wang,
Ernest S. Kuh:
A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction.
DATE 1998: 466-470 |
| 49 | EE | Qingjian Yu,
Janet Meiling Wang,
Ernest S. Kuh:
Multipoint moment matching model for multiport distributed interconnect networks.
ICCAD 1998: 85-91 |
| 48 | EE | Hiroshi Murata,
Ernest S. Kuh:
Sequence-pair based placement method for hard/soft/pre-placed modules.
ISPD 1998: 167-172 |
| 1997 |
|---|
| 47 | EE | Ernest S. Kuh:
Physical design: reminiscing and looking ahead.
ISPD 1997: 206 |
| 46 | EE | Premal Buch,
Ernest S. Kuh:
SYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits.
VLSI Design 1997: 403-407 |
| 45 | EE | Henrik Esbensen,
Ernest S. Kuh:
A performance-driven IC/MCM placement algorithm featuring explicit design space exploration.
ACM Trans. Design Autom. Electr. Syst. 2(1): 62-80 (1997) |
| 44 | EE | Xianlong Hong,
Tianxiong Xue,
Jin Huang,
Chung-Kuan Cheng,
Ernest S. Kuh:
TIGER: an efficient timing-driven global router for gate array and standard cell layout design.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1323-1331 (1997) |
| 43 | EE | Tianxiong Xue,
Ernest S. Kuh,
Dongsheng Wang:
Post global routing crosstalk synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(12): 1418-1430 (1997) |
| 1996 |
|---|
| 42 | EE | Dongsheng Wang,
Ernest S. Kuh:
Performance-Driven Interconnect Global Routing.
Great Lakes Symposium on VLSI 1996: 132-136 |
| 41 | EE | Tianxiong Xue,
Ernest S. Kuh,
Dongsheng Wang:
Post global routing crosstalk risk estimation and reduction.
ICCAD 1996: 302-309 |
| 40 | EE | Jun-Fa Mao,
Janet Meiling Wang,
Ernest S. Kuh:
Simulation and sensitivity analysis of transmission line circuits by the characteristics method.
ICCAD 1996: 556-562 |
| 39 | EE | Qingjian Yu,
Ernest S. Kuh,
Tianxiong Xue:
Moment models of general transmission lines with application to interconnect analysis and optimization.
IEEE Trans. VLSI Syst. 4(4): 477-494 (1996) |
| 1995 |
|---|
| 38 | EE | Tianxiong Xue,
Ernest S. Kuh:
Post routing performance optimization via tapered link insertion and wiresizing.
EURO-DAC 1995: 74-79 |
| 37 | EE | Tianxiong Xue,
Ernest S. Kuh:
Post routing performance optimization via multi-link insertion and non-uniform wiresizing.
ICCAD 1995: 575-580 |
| 36 | EE | Premal Buch,
Shen Lin,
Vijay Nagasamy,
Ernest S. Kuh:
Techniques for fast circuit simulation applied to power estimation of CMOS circuits.
ISLPD 1995: 135-138 |
| 35 | EE | Qingjian Yu,
Ernest S. Kuh:
Exact moment matching model of transmission lines and application to interconnect delay estimation.
IEEE Trans. VLSI Syst. 3(2): 311-322 (1995) |
| 34 | EE | Akira Onozawa,
Kamal Chaudhary,
Ernest S. Kuh:
Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(6): 707-719 (1995) |
| 1993 |
|---|
| 33 | EE | Xianlong Hong,
Tianxiong Xue,
Ernest S. Kuh,
Chung-Kuan Cheng,
Jin Huang:
Performance-Driven Steiner Tree Algorithm for Global Routing.
DAC 1993: 177-181 |
| 32 | EE | Jin Huang,
Xianlong Hong,
Chung-Kuan Cheng,
Ernest S. Kuh:
An Efficient Timing-Driven Global Routing Algorithm.
DAC 1993: 596-600 |
| 31 | EE | Minshine Shih,
Ernest S. Kuh:
Quadratic Boolean Programming for Performance-Driven System Partitioning.
DAC 1993: 761-765 |
| 30 | EE | Kamal Chaudhary,
Akira Onozawa,
Ernest S. Kuh:
A spacing algorithm for performance enhancement and cross-talk reduction.
ICCAD 1993: 697-702 |
| 29 | | Tianxiong Xue,
Takashi Fujii,
Ernest S. Kuh:
A new performance-driven global routing algorithm for gate array.
VLSI 1993: 321-330 |
| 28 | | Shen Lin,
Ernest S. Kuh:
Circuit simulation for large interconnected IC networks.
VLSI 1993: 333-342 |
| 27 | EE | Shen Lin,
Ernest S. Kuh,
Malgorzata Marek-Sadowska:
Stepwise equivalent conductance circuit simulation technique.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 672-683 (1993) |
| 1992 |
|---|
| 26 | EE | Takashi Mitsuhashi,
Ernest S. Kuh:
Power and Ground Network Topology Optimization for Cell Based VLSIs.
DAC 1992: 524-529 |
| 25 | EE | Minshine Shih,
Ernest S. Kuh,
Ren-Song Tsay:
Performance-Driven System Partitioning on Multi-Chip Modules.
DAC 1992: 53-56 |
| 24 | EE | Xianlong Hong,
Jin Huang,
Chung-Kuan Cheng,
Ernest S. Kuh:
FARM: An Efficient Feed-Through Pin Assignment Algorithm.
DAC 1992: 530-535 |
| 23 | EE | Shen Lin,
Ernest S. Kuh:
Transient Simulation of Lossy Interconnect.
DAC 1992: 81-86 |
| 1991 |
|---|
| 22 | | Arvind Srinivasan,
Kamal Chaudhary,
Ernest S. Kuh:
RITUAL: Performance Driven Placement Algorithm for Small Cell ICs.
ICCAD 1991: 48-51 |
| 21 | | Massoud Pedram,
Kamal Chaudhary,
Ernest S. Kuh:
I/O Pad Assignment Based on the Circuit Structure.
ICCD 1991: 314-318 |
| 1990 |
|---|
| 20 | EE | Shen Lin,
Malgorzata Marek-Sadowska,
Ernest S. Kuh:
Delay and Area Optimization in Standard-Cell Design.
DAC 1990: 349-352 |
| 19 | EE | Michael A. B. Jackson,
Arvind Srinivasan,
Ernest S. Kuh:
Clock Routing for High-Performance ICs.
DAC 1990: 573-579 |
| 18 | EE | Arvind Srinivasan,
Ernest S. Kuh:
MOLE: a sea-of-gates detailed router.
EURO-DAC 1990: 446-450 |
| 17 | | Michael A. B. Jackson,
Arvind Srinivasan,
Ernest S. Kuh:
A Fast Algorithm for Performance-Driven Placement.
ICCAD 1990: 328-331 |
| 16 | | Massoud Pedram,
Malgorzata Marek-Sadowska,
Ernest S. Kuh:
Floorplanning with Pin Assignment.
ICCAD 1990: 98-101 |
| 15 | | Kwang-Ting Cheng,
Vishwani D. Agrawal,
Ernest S. Kuh:
A Simulation-Based Method for Generating Tests for Sequential Circuits.
IEEE Trans. Computers 39(12): 1456-1463 (1990) |
| 1989 |
|---|
| 14 | EE | Michael A. B. Jackson,
Ernest S. Kuh:
Performance-driven Placement of Cell Based IC's.
DAC 1989: 370-375 |
| 1988 |
|---|
| 13 | EE | Ren-Song Tsay,
Ernest S. Kuh,
Chi-Ping Hsu:
Proud: A Fast Sea-of-Gates Placement Algorithm.
DAC 1988: 318-323 |
| 12 | EE | Xiao-Ming Xiong,
Ernest S. Kuh:
The Constrained Via Minimization Problem for PCB and VLSI Design.
DAC 1988: 573-578 |
| 1987 |
|---|
| 11 | EE | Xiao-Ming Xiong,
Ernest S. Kuh:
Nutcracker: An Efficient and Intelligent Channel Spacer.
DAC 1987: 298-304 |
| 10 | EE | Wayne Wei-Ming Dai,
Masao Sato,
Ernest S. Kuh:
A Dynamic and Efficient Representation of Building-Block Layout.
DAC 1987: 376-384 |
| 9 | EE | Wayne Wei-Ming Dai,
Ernest S. Kuh:
Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 828-837 (1987) |
| 1986 |
|---|
| 8 | EE | Howard H. Chen,
Ernest S. Kuh:
Glitter: A Gridless Variable-Width Channel Router.
IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 459-465 (1986) |
| 1985 |
|---|
| 7 | EE | Wayne Wei-Ming Dai,
Tetsuo Asano,
Ernest S. Kuh:
Routing Region Definition and Ordering Scheme for Building-Block Layout.
IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 189-197 (1985) |
| 1984 |
|---|
| 6 | EE | Tom Tsan-Kuo Tarng,
Malgorzata Marek-Sadowska,
Ernest S. Kuh:
An Efficient Single-Row Routing Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 178-183 (1984) |
| 5 | EE | Chung-Kuan Cheng,
Ernest S. Kuh:
Module Placement Based on Resistive Network Optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 218-225 (1984) |
| 1983 |
|---|
| 4 | EE | Shuji Tsukiyama,
Ernest S. Kuh,
Isao Shirakawa:
On the Layering Problem of Multilayer PWB Wiring.
IEEE Trans. on CAD of Integrated Circuits and Systems 2(1): 30-38 (1983) |
| 3 | EE | Ernest S. Kuh:
Editorial: Routing in Microelectronics.
IEEE Trans. on CAD of Integrated Circuits and Systems 2(4): 213-214 (1983) |
| 1982 |
|---|
| 2 | EE | Takeshi Yoshimura,
Ernest S. Kuh:
Efficient Algorithms for Channel Routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 1(1): 25-35 (1982) |
| 1980 |
|---|
| 1 | | Shuji Tsukiyama,
Ernest S. Kuh,
Isao Shirakawa:
On the layering problem of multilayer PWB wiring.
Graph Theory and Algorithms 1980: 20-37 |
