| 2008 |
|---|
| 62 | EE | Xingguo Xiong,
Yu-Liang Wu,
Wen-Ben Jone:
Material Fatigue and Reliability of MEMS Accelerometers.
DFT 2008: 314-322 |
| 61 | EE | Hao Xu,
Wen-Ben Jone,
Ranga Vemuri:
Accurate energy breakeven time estimation for run-time power gating.
ICCAD 2008: 161-168 |
| 60 | EE | Hao Xu,
Ranga Vemuri,
Wen-Ben Jone:
Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW.
ICCD 2008: 618-625 |
| 59 | EE | Hao Xu,
Ranga Vemuri,
Wen-Ben Jone:
Dynamic virtual ground voltage estimation for power gating.
ISLPED 2008: 27-32 |
| 2007 |
|---|
| 58 | EE | Jianxun Liu,
Wen-Ben Jone:
An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects.
ICCD 2007: 360-367 |
| 57 | EE | Wei Pei,
Wen-Ben Jone,
Yiming Hu:
Fault Modeling and Detection for Drowsy SRAM Caches.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1084-1100 (2007) |
| 2006 |
|---|
| 56 | EE | Ming Li,
Qing-An Zeng,
Wen-Ben Jone:
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip.
DAC 2006: 849-852 |
| 55 | EE | Xingguo Xiong,
Yu-Liang Wu,
Wen-Ben Jone:
Reliability Analysis of Self-Repairable MEMS Accelerometer.
DFT 2006: 236-244 |
| 54 | EE | Ming Li,
Wen-Ben Jone,
Qing-An Zeng:
An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing.
ISVLSI 2006: 147-152 |
| 2005 |
|---|
| 53 | EE | Cheng-Hung Lin,
Yung-Chang Huang,
Shih-Chieh Chang,
Wen-Ben Jone:
Design and design automation of rectification logic for engineering change.
ASP-DAC 2005: 1006-1009 |
| 52 | EE | Xingguo Xiong,
Yu-Liang Wu,
Wen-Ben Jone:
Design and Analysis of Self-Repairable MEMS Accelerometer.
DFT 2005: 21-32 |
| 2004 |
|---|
| 51 | EE | S. Ghosh,
K. W. Lai,
Wen-Ben Jone,
Shih-Chieh Chang:
Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits.
Asian Test Symposium 2004: 210-215 |
| 50 | | Rui Min,
Wen-Ben Jone,
Yiming Hu:
Phased tag cache: an efficient low power cache system.
ISCAS (2) 2004: 805-808 |
| 49 | EE | Rui Min,
Wen-Ben Jone,
Yiming Hu:
Location cache: a low-power L2 cache system.
ISLPED 2004: 120-125 |
| 48 | EE | Rui Min,
Zhiyong Xu,
Yiming Hu,
Wen-Ben Jone:
Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs.
VLSI Design 2004: 183-188 |
| 47 | EE | Xingguo Xiong,
Yu-Liang Wu,
Wen-Ben Jone:
A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices.
VTS 2004: 148-153 |
| 2003 |
|---|
| 46 | EE | Wen-Ben Jone,
Jinn-Shyan Wang,
Hsueh-I Lu,
I. P. Hsu,
J.-Y. Chen:
Design theory and implementation for low-power segmented bus systems.
ACM Trans. Design Autom. Electr. Syst. 8(1): 38-54 (2003) |
| 45 | EE | J. H. Jiang,
Wen-Ben Jone,
Shih-Chieh Chang,
S. Ghosh:
Embedded core test generation using broadcast test architecture and netlist scrambling.
IEEE Transactions on Reliability 52(4): 435-443 (2003) |
| 2002 |
|---|
| 44 | EE | Wen-Ben Jone,
Der-Cheng Huang,
S. C. Wu,
K. J. Lee:
An efficient BIST method for distributed small buffers.
IEEE Trans. VLSI Syst. 10(4): 512-515 (2002) |
| 43 | EE | Der-Cheng Huang,
Wen-Ben Jone:
A parallel built-in self-diagnostic method for embedded memoryarrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 449-465 (2002) |
| 42 | EE | Der-Cheng Huang,
Wen-Ben Jone:
A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 617-628 (2002) |
| 2001 |
|---|
| 41 | EE | J. H. Jiang,
Shih-Chieh Chang,
Wen-Ben Jone:
Embedded Core Testing Using Broadcast Test Architecture.
DFT 2001: 95-103 |
| 40 | EE | Der-Cheng Huang,
Wen-Ben Jone,
Sunil R. Das:
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers.
VLSI Design 2001: 379-384 |
| 39 | EE | Der-Cheng Huang,
Wen-Ben Jone,
Sunil R. Das:
A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers.
VLSI Design 2001: 397-402 |
| 38 | EE | Shih-Chieh Chang,
Ching-Hwa Cheng,
Wen-Ben Jone,
Shin-De Lee,
Jinn-Shyan Wang:
Charge-sharing alleviation and detection for CMOS domino circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 266-280 (2001) |
| 2000 |
|---|
| 37 | EE | Der-Cheng Huang,
Wen-Ben Jone:
An efficient parallel transparent diagnostic BIST.
Asian Test Symposium 2000: 299- |
| 36 | EE | Ching-Hwa Cheng,
Wen-Ben Jone,
Jinn-Shyan Wang,
Shih-Chieh Chang:
Charge sharing fault analysis and testing for CMOS domino logic circuits.
Asian Test Symposium 2000: 435-440 |
| 35 | EE | Ching-Hwa Cheng,
Jinn-Shyan Wang,
Shih-Chieh Chang,
Wen-Ben Jone:
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits.
DFT 2000: 329-337 |
| 34 | | Ching-Hwa Cheng,
Shih-Chieh Chang,
Shin-De Li,
Wen-Ben Jone,
Jinn-Shyan Wang:
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation.
ICCAD 2000: 387-390 |
| 33 | EE | Shih-Chieh Chang,
Wen-Ben Jone,
Shi-Sen Chang:
TAIR: testability analysis by implication reasoning.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 152-160 (2000) |
| 1999 |
|---|
| 32 | EE | Ching-Wei Yeh,
Min-Cheng Chang,
Shih-Chieh Chang,
Wen-Ben Jone:
Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications.
DAC 1999: 68-71 |
| 31 | EE | Ching-Hwa Cheng,
Shih-Chieh Chang,
Jinn-Shyan Wang,
Wen-Ben Jone:
Charge Sharing Fault Detection for CMOS Domino Logic Circuits.
DFT 1999: 77-85 |
| 30 | EE | Chingwei Yeh,
Min-Cheng Chang,
Shih-Chieh Chang,
Wen-Ben Jone:
Power reduction through iterative gate sizing and voltage scaling.
ISCAS (1) 1999: 246-249 |
| 29 | EE | Wen-Ben Jone,
Der-Cheng Huang,
S. C. Wu,
K. J. Lee:
An Efficient BIST Method for Small Buffers.
VTS 1999: 246-251 |
| 28 | EE | J.-Y. Chen,
Wen-Ben Jone,
Jinn-Shyan Wang,
Hsueh-I Lu,
T. F. Chen:
Segmented bus design for low-power systems.
IEEE Trans. VLSI Syst. 7(1): 25-29 (1999) |
| 1998 |
|---|
| 27 | EE | Wen-Ben Jone,
Jiann-Chyi Rau,
Shih-Chieh Chang,
Yu-Liang Wu:
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits.
ITC 1998: 322-330 |
| 26 | EE | Shih-Chieh Chang,
Shi-Sen Chang,
Wen-Ben Jone,
Chien-Chung Tsai:
A novel combinational testability analysis by considering signal correlation.
ITC 1998: 658-667 |
| 25 | EE | Wen-Ben Jone,
Sunil R. Das:
A Stochastic Method for Defect Level Analysis of Pseudorandom Testing.
VLSI Design 1998: 382- |
| 24 | EE | Wen-Ben Jone,
K. S. Tsai:
Confidence analysis for defect-level estimation of VLSI random testing.
ACM Trans. Design Autom. Electr. Syst. 3(3): 389-407 (1998) |
| 1997 |
|---|
| 23 | EE | Wen-Ben Jone,
Yun-Pan Ho,
Sunil R. Das:
Delay Fault Coverage Enhancement Using Multiple Test Observation Times.
VLSI Design 1997: 106-110 |
| 22 | EE | Wen-Ben Jone,
Yun-Pan Ho,
Sunil R. Das:
Delay Fault Coverage Enhancement Using Variable Observation Times.
J. Electronic Testing 11(2): 131-146 (1997) |
| 1996 |
|---|
| 21 | EE | Sunil R. Das,
N. Goel,
Wen-Ben Jone,
A. R. Nayak:
Syndrome signature in output compaction for VLSI BIST.
VLSI Design 1996: 337-338 |
| 20 | EE | Dan Li,
Wen-Ben Jone:
Pseudorandom test-length analysis using differential solutions.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(7): 815-825 (1996) |
| 1995 |
|---|
| 19 | EE | Sunil R. Das,
H. T. Ho,
Wen-Ben Jone,
A. R. Nayak:
An improved output compaction technique for built-in self-test in VLSI circuits.
VLSI Design 1995: 403-407 |
| 18 | EE | Wen-Ben Jone,
Paresh Gondalia,
Allan Gutjahr:
Realizing a high measure of confidence for defect level analysis of random testing [VLSI].
IEEE Trans. VLSI Syst. 3(3): 446-450 (1995) |
| 17 | EE | Chen-Liang Fang,
Wen-Ben Jone:
Timing optimization by gate resizing and critical path identification.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 201-217 (1995) |
| 16 | EE | Wen-Ben Jone,
Christos A. Papachristou:
A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 374-384 (1995) |
| 1994 |
|---|
| 15 | | A. R. Nayak,
Wen-Ben Jone,
Sunil R. Das:
Designing General-Purpose Fault-Tolerant Distributed Systems - A Layered Approach.
ICPADS 1994: 360-365 |
| 14 | | Sunil R. Das,
Wen-Ben Jone,
Amiya Nayak,
Ian Choi:
On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition.
VLSI Design 1994: 311-314 |
| 13 | | Wen-Ben Jone,
Cheng-Juei Wu:
Multiple Fault Detection in Parity Checkers.
IEEE Trans. Computers 43(9): 1096-1099 (1994) |
| 1993 |
|---|
| 12 | EE | Wen-Ben Jone,
Chen-Liang Fang:
Timing Optimization By Gate Resizing And Critical Path Identification.
DAC 1993: 135-140 |
| 11 | | Cheng-Juei Wu,
Wen-Ben Jone:
On Multiple Fault Detection of Parity Checkers.
ISCAS 1993: 1515-1518 |
| 10 | | Paresh Gondalia,
Allan Gutjahr,
Wen-Ben Jone:
Realizing a High Measure of Confidence for Defect Level Analysis of Random Testing.
ITC 1993: 478-487 |
| 9 | | Wen-Ben Jone,
Sunil R. Das:
CACOP - A Random Pattern Testability Analyzer.
VLSI Design 1993: 61-64 |
| 8 | EE | Wen-Ben Jone,
Patrick H. Madden:
Multiple fault testing using minimal single fault test set for fanout-free circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 149-157 (1993) |
| 7 | EE | Wen-Ben Jone:
Defect level estimation of circuit testing using sequential statistical analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(2): 336-348 (1993) |
| 1991 |
|---|
| 6 | | Anita Gleason,
Wen-Ben Jone:
Reduced Hamming Count and Its Aliasing Probability.
ICCD 1991: 356-359 |
| 5 | | Wen-Ben Jone:
Defect Level Estimation of Random and Pseudorandom Testing.
ITC 1991: 712-721 |
| 4 | EE | Wen-Ben Jone,
Anita Gleason:
Analysis of Hamming count compaction scheme.
J. Electronic Testing 2(4): 373-384 (1991) |
| 1990 |
|---|
| 3 | EE | Wen-Ben Jone,
Sunil R. Das:
Multiple-output parity bit signature for exhaustive testing.
J. Electronic Testing 1(2): 175-178 (1990) |
| 1989 |
|---|
| 2 | EE | Wen-Ben Jone,
Christos A. Papachristou:
A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing.
DAC 1989: 525-534 |
| 1 | EE | Wen-Ben Jone,
Christos A. Papachristou,
M. Pereira:
A Scheme for Overlaying Concurrent Testing of VLSI Circuits.
DAC 1989: 531-536 |
