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Welson Sun

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2007
3EEWelson Sun, Michael J. Wirthlin, Stephen Neuendorffer: FPGA Pipeline Synthesis Design Exploration Using Module Selection and Resource Sharing. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 254-265 (2007)
2006
2EEMichael J. Wirthlin, Welson Sun: DSynth: A Pipeline Synthesis Environment for FPGAs. FCCM 2006: 343-344
1EEWelson Sun, Michael J. Wirthlin, Stephen Neuendorffer: Combining module selection and resource sharing for efficient FPGA pipeline synthesis. FPGA 2006: 179-188

Coauthor Index

1Stephen Neuendorffer [1] [3]
2Michael J. Wirthlin [1] [2] [3]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)