| |
| 2008 | ||
|---|---|---|
| 7 | EE | Sanghyeon Baeg: Low Power Configuration Strategy of TCAM Lookup Table. IEICE Transactions 91-B(3): 915-917 (2008) |
| 2007 | ||
| 6 | EE | Sanghyeon Baeg: Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2215-2221 (2007) |
| 2005 | ||
| 5 | EE | Sanghyeon Baeg, Sung Soo Chung: Analytical test buffer design for differential signaling I/O buffers by error syndrome analysis. IEEE Trans. VLSI Syst. 13(3): 370-383 (2005) |
| 2001 | ||
| 4 | Sung Soo Chung, Sanghyeon Baeg: AC-JTAG: empowering JTAG beyond testing DC nets. ITC 2001: 30-37 | |
| 1999 | ||
| 3 | EE | Sanghyeon Baeg, William A. Rogers: A cost-effective design for testability: clock line control and test generation using selective clocking. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 850-861 (1999) |
| 1994 | ||
| 2 | Sanghyeon Baeg, William A. Rogers: A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits. ICCD 1994: 354-358 | |
| 1 | Sanghyeon Baeg, William A. Rogers: Hybrid Design for Testability Combining Scan and Clock Line Control and Method for Test Generation. ITC 1994: 340-349 | |
| 1 | Sung Soo Chung | [4] [5] |
| 2 | William A. Rogers | [1] [2] [3] |