2009 | ||
---|---|---|
54 | EE | Deming Chen, Russell Tessier, Mojy C. Chian, Steve Trimberger, Shinobu Fujita, André DeHon, Deming Chen: CMOS vs Nano: comrades or rivals? FPGA 2009: 121-122 |
53 | EE | Raphael Rubin, André DeHon: Choose-your-own-adventure routing: lightweight load-time defect avoidance. FPGA 2009: 23-32 |
52 | EE | Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon: Pipelining Saturated Accumulation. IEEE Trans. Computers 58(2): 208-219 (2009) |
2008 | ||
51 | EE | André DeHon, Mike Hutton: Guest Editorial: TRETS Special Edition on the 15th International Symposium on FPGAs. TRETS 1(1): (2008) |
2007 | ||
50 | André DeHon, Mike Hutton: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007 ACM 2007 | |
49 | André DeHon, Jean-Louis Giavitto, Frédéric Gruau: Computing Media and Languages for Space-Oriented Computation, 03.09. - 08.09.2006 Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany 2007 | |
48 | EE | André DeHon, Jean-Louis Giavitto, Frédéric Gruau: 06361 Abstracts Collection -- Computing Media Languages for Space-Oriented Computation. Computing Media and Languages for Space-Oriented Computation 2007 |
47 | EE | André DeHon, Jean-Louis Giavitto, Frédéric Gruau: 06361 Executive Report -- Computing Media Languages for Space-Oriented Computation. Computing Media and Languages for Space-Oriented Computation 2007 |
46 | EE | Helia Naeimi, André DeHon: Fault Secure Encoder and Decoder for Memory Applications. DFT 2007: 409-417 |
45 | EE | Nachiket Kapre, André DeHon: Optimistic Parallelization of Floating-Point Accumulation. IEEE Symposium on Computer Arithmetic 2007: 205-216 |
44 | EE | André DeHon, Craig S. Lent, Fabrizio Lombardi: Introduction to the Special Section on Nano Systems and Computing. IEEE Trans. Computers 56(2): 145-146 (2007) |
43 | EE | Kia Bazargan, André DeHon: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 201-202 (2007) |
2006 | ||
42 | Steven J. E. Wilton, André DeHon: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006 ACM 2006 | |
41 | EE | Michael G. Wrighton, André DeHon: SAT-based optimal hypergraph partitioning with replication. ASP-DAC 2006: 789-795 |
40 | EE | Michael DeLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomas E. Uribe, Thomas F. Knight Jr., André DeHon: GraphStep: A System Architecture for Sparse-Graph Algorithms. FCCM 2006: 143-151 |
39 | EE | Nachiket Kapre, Nikil Mehta, Michael DeLorimier, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael G. Wrighton, André DeHon: Packet Switched vs. Time Multiplexed FPGA Overlay Networks. FCCM 2006: 205-216 |
38 | EE | Rajiv V. Joshi, Kaustav Banerjee, André DeHon: Tutorial 1: Emerging Technologies for VLSI Design. ISQED 2006: 4 |
37 | EE | John E. Savage, Eric Rachlin, André DeHon, Charles M. Lieber, Yue Wu: Radial addressing of nanowires. JETC 2(2): 129-154 (2006) |
36 | EE | André DeHon, Randy Huang, John Wawrzynek: Stochastic spatial routing for reconfigurable networks. Microprocessors and Microsystems 30(6): 301-318 (2006) |
35 | EE | André DeHon, Yury Markovskiy, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek: Stream computations organized for reconfigurable execution. Microprocessors and Microsystems 30(6): 334-354 (2006) |
2005 | ||
34 | EE | André DeHon: Design of programmable interconnect for sublithographic programmable logic arrays. FPGA 2005: 127-137 |
33 | EE | Michael DeLorimier, André DeHon: Floating-point sparse matrix-vector multiply for FPGAs. FPGA 2005: 75-85 |
32 | Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon: Pipelining Saturated Accumulation. FPT 2005: 19-26 | |
31 | André DeHon, Konstantin Likharev: Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation. ICCAD 2005: 375-382 | |
30 | EE | André DeHon, Helia Naeimi: Seven Strategies for Tolerating Highly Defective Fabrication. IEEE Design & Test of Computers 22(4): 306-315 (2005) |
29 | EE | André DeHon: Nanowire-based programmable architectures. JETC 1(2): 109-162 (2005) |
2004 | ||
28 | EE | André DeHon, Joshua Adams, Michael DeLorimier, Nachiket Kapre, Yuki Matsuda, Helia Naeimi, Michael C. Vanier, Michael G. Wrighton: Design Patterns for Reconfigurable Computing. FCCM 2004: 13-23 |
27 | EE | André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica: What is the right model for programming and using modern FPGAs? FPGA 2004: 119 |
26 | EE | André DeHon, Michael J. Wilson: Nanowire-based sublithographic programmable logic arrays. FPGA 2004: 123-132 |
25 | EE | André DeHon, Raphael Rubin: Design of FPGA interconnect for multilevel metallization. IEEE Trans. VLSI Syst. 12(10): 1038-1050 (2004) |
24 | EE | André DeHon: Unifying mesh- and tree-based programmable interconnect. IEEE Trans. VLSI Syst. 12(10): 1051-1065 (2004) |
2003 | ||
23 | EE | Raphael Rubin, André DeHon: Design of FPGA interconnect for multilevel metalization. FPGA 2003: 154-163 |
22 | EE | Michael G. Wrighton, André DeHon: Hardware-assisted simulated annealing with application for fast FPGA placement. FPGA 2003: 33-42 |
21 | EE | Randy Huang, John Wawrzynek, André DeHon: Stochastic, spatial routing for hypergraphs, trees, and meshes. FPGA 2003: 78-87 |
2002 | ||
20 | EE | André DeHon, Randy Huang, John Wawrzynek: Hardware-Assisted Fast Routing. FCCM 2002: 205- |
19 | EE | Yury Markovskiy, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon: Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. FPGA 2002: 196-205 |
18 | EE | Michael Butts, André DeHon, Seth Copen Goldstein: Molecular electronics: devices, systems and tools for gigagate, gigabit chips. ICCAD 2002: 433-440 |
17 | EE | André DeHon: Very Large Scale Spatial Computing. UMC 2002: 27-36 |
2001 | ||
16 | EE | André DeHon: Rent's rule based switching requirements. SLIP 2001: 197-204 |
2000 | ||
15 | EE | Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon: Stream Computations Organized for Reconfigurable Execution (SCORE). FPL 2000: 605-614 |
14 | EE | André DeHon: Compact, multilayer layout for butterfly fat-tree. SPAA 2000: 206-215 |
13 | André DeHon: The Density Advantage of Configurable Computing. IEEE Computer 33(4): 41-49 (2000) | |
1999 | ||
12 | EE | André DeHon, John Wawrzynek: Reconfigurable Computing: What, Why, and Implications for Design Automation. DAC 1999: 610-615 |
11 | EE | William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, George Varghese, John Wawrzynek, André DeHon: HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array. FPGA 1999: 125-134 |
10 | EE | André DeHon: Balancing Interconnect and Computation in a Reconfiguable Computing Array (or, why you don't really want 100% LUT utilization). FPGA 1999: 69-78 |
1998 | ||
9 | EE | Michael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, John Wawrzynek: Object Oriented Circuit-Generators in Java. FCCM 1998: 158-166 |
8 | EE | Timothy J. Callahan, Philip Chong, André DeHon, John Wawrzynek: Fast Module Mapping and Placement for Datapaths in FPGAs. FPGA 1998: 123-132 |
1997 | ||
7 | EE | André DeHon: Directions in General-Purpose Computing Architectures. HICSS (1) 1997: 717-718 |
6 | William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg: Seeking Solutions in Configurable Computing. IEEE Computer 30(12): 38-43 (1997) | |
1996 | ||
5 | EE | André DeHon: DPGA Utilization and Application. FPGA 1996: 115-121 |
4 | EE | André DeHon: Entropy, Counting, and Programmable Interconnect. FPGA 1996: 73-79 |
1994 | ||
3 | Frederic T. Chong, Henry Minsky, André DeHon, Matthew Becker, Samuel Peretz, Eran Egozy, Thomas F. Knight Jr.: METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks. ISCA 1994: 266-277 | |
2 | André DeHon: In-System Timing Extraction and Control Through Scan-Based, Test-Access Ports. ITC 1994: 350-359 | |
1 | Ian Eslick, André DeHon, Thomas F. Knight Jr.: Guaranteeing Idempotence for Tightly-Coupled, Fault-Tolerant Networks. PCRCW 1994: 215-225 |