Jinian Bian

2009
39	EE	Liu Dawei, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong: Cell shifting aware of wirelength and overlap. ISQED 2009: 506-510
2008
38	EE	Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto: HyMacs: hybrid memory access optimization based on custom-instruction scheduling. ACM Great Lakes Symposium on VLSI 2008: 89-94
37	EE	Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian: Low power clock buffer planning methodology in F-D placement for large scale circuit design. ASP-DAC 2008: 370-375
36	EE	Kang Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, Satoshi Goto: Cache miss reduction through hardware-assisted loop optimization. CSCWD 2008: 129-134
35	EE	Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong: MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. FPL 2008: 559-562
34	EE	Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng: A novel fixed-outline floorplanner with zero deadspace for hierarchical design. ICCAD 2008: 16-23
33	EE	Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto: Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration. ISQED 2008: 321-324
32	EE	Kun Tong, Jinian Bian, Haili Wang: A cooperative universal data model platform for the data-centric electronic system-level design. Advanced Engineering Informatics 22(3): 296-306 (2008)
31	EE	Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto: Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design. IEICE Transactions 91-A(6): 1478-1487 (2008)
30	EE	Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto: Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System. IEICE Transactions 91-A(9): 2456-2464 (2008)
2007
29	EE	Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong: An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI 2007: 564-569
28	EE	Hui Zhang, Jinian Bian: A Management System of Metropolis Energy Information. CSCWD 2007: 1066-1071
27	EE	Kang Zhao, Jinian Bian, Sheqin Dong: A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. CSCWD 2007: 121-126
26	EE	Shujun Deng, Jinian Bian, Weimin Wu, Xiaoqing Yang, Yanni Zhao: EHSAT: An Efficient RTL Satisfiability Solver Using an Extended DPLL Procedure. DAC 2007: 588-593
25	EE	Zhipeng Liu, Jinian Bian, Qiang Zhou, Hui Dai: Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan. ISVLSI 2007: 279-284
24	EE	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng: Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 645-658 (2007)
2006
23	EE	Kang Zhao, Jinian Bian: A Clustering ILP Model for Fast Instruction Selection in Embedded Applicated Specific Processor Design. APCCAS 2006: 1160-1163
22	EE	Liang Zhu, Jinian Bian: From Software to Hardware - A Novel TLM Auto-Generating Method. APCCAS 2006: 1725-1728
21	EE	Zhen Zhao, Jinian Bian, Zhipeng Liu, Yunfeng Wang, Kang Zhao: High Level Synthesis with Multiple supply Voltages for Energy and Combined Peak Power Minimization. APCCAS 2006: 864-867
20	EE	Kun Tong, Jinian Bian, Haili Wang: Universal data model platform: the data-centric evolution for system level codesign. CSCWD 2006: 1037-1042
19	EE	Yawen Niu, Jinian Bian, Haili Wang, Kun Tong, Liang Zhu: AGOM: A Novel Method of Embedded System Communication Architecture Design in System Level Design. CSCWD 2006: 324-329
18	EE	Shujun Deng, Weimin Wu, Jinian Bian: Cooperative Bounded Model Checking Using STE and Hybrid Three-Valued SAT Solving. CSCWD 2006: 522-528
17	EE	Yawen Niu, Jinian Bian, Haili Wang, Kun Tong: An Efficient Cooperative Design Framework for SOC On-Chip Communication Architecture System-Level Design. CSCWD (Selected Papers) 2006: 118-127
16	EE	Shujun Deng, Weimin Wu, Jinian Bian: Bounded Model Checking Combining Symbolic Trajectory Evaluation Abstraction with Hybrid Three-Valued SAT Solving. CSCWD (Selected Papers) 2006: 297-307
15	EE	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng: Integrating dynamic thermal via planning with 3D floorplanning algorithm. ISPD 2006: 178-185
14	EE	Kang Zhao, Jinian Bian, Sheqin Dong: A Heterogeneous Dependency Graph as Intermediate Representation for Instruction Set Customization. JCIS 2006
13	EE	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani: Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. ACM Trans. Design Autom. Electr. Syst. 11(2): 325-345 (2006)
2005
12	EE	Qiang Wu, Jinian Bian, Hongxi Xue: System-level architectural exploration using allocation-on-demand technique. ASP-DAC 2005: 1296-1298
11		Feng Lin, Haili Wang, Jinian Bian: HW/SW Interface Synthesis Based on Avalon Bus Specification for Nios-Oriented SoC Design. FPT 2005: 305-306
10	EE	Yunfeng Wang, Jinian Bian, Xianlong Hong, Liu Yang, Qiang Zhou, Qiang Wu: A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. ICESS 2005: 275-286
9	EE	Yunfeng Wang, Jinian Bian, Xianlong Hong: Interconnect delay optimization via high level re-synthesis after floorplanning. ISCAS (6) 2005: 5641-5644
8	EE	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani: A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) 2005: 6230-6233
2004
7	EE	Jianzhou Zhao, Jinian Bian, Weimin Wu: PFGASAT- A Genetic SAT Solver Combining Partitioning and Fuzzy Strategie. COMPSAC 2004: 108-113
6	EE	Qiang Wu, Jinian Bian, Hongxi Xue: A Distributed Architecture Model for Heterogeneous Multiprocessor System-on-Chip Design. ICESS 2004: 150-157
5	EE	Ming Zhu, Jinian Bian, Weimin Wu: Model Optimization Techniques in a Verification Platform for Classified Properties. ICESS 2004: 542-548
4	EE	Haili Wang, Jinian Bian, Yawen Niu, Kun Tong, Yunfeng Wang: CA-Ex: A Tuning-Incremental Methodology for Communication Architectures in Embedded Systems. ICESS 2004: 74-80
2003
3	EE	Ming Zhu, Jinian Bian, Weimin Wu, Hongxi Xue: Property Classification for Functional Verification Based. Asian Test Symposium 2003: 503
2000
2	EE	Wangning Long, Yu-Liang Wu, Jinian Bian: IBAW: an implication-tree based alternative-wiring logic transformation algorithm. ASP-DAC 2000: 415-422
1999
1	EE	Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong: FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking. ASP-DAC 1999: 363-

Coauthor Index

1	Jinsong Bei	[1]
2	Yici Cai	[8] [35] [37] [39]
3	Juanjuan Chen	[35]
4	Chung-Kuan Cheng	[15] [24] [34]
5	Hui Dai	[25]
6	Liu Dawei	[39]
7	Shujun Deng	[16] [18] [26]
8	Sheqin Dong	[14] [27] [29] [30] [31] [33] [34] [36] [38]
9	Satoshi Goto	[30] [31] [33] [34] [36] [38]
10	Ou He	[29] [34]
11	Xianlong Hong	[1] [8] [9] [10] [13] [15] [24] [29] [35] [37] [39]
12	Jiang Hu	[37]
13	Chenqian Jiang	[36]
14	Hongxing Li	[1]
15	Zhuoyuan Li	[8] [13] [15] [24]
16	Feng Lin	[11]
17	Zhipeng Liu	[21] [25]
18	Wangning Long	[2]
19	Yuchun Ma	[29]
20	Yawen Niu	[4] [17] [19]
21	Vijay Pitchumani	[8] [13] [15] [24]
22	Prashant Saxena	[8]
23	Yang Song	[30] [31] [33] [38]
24	Kun Tong	[4] [17] [19] [20] [32]
25	Haili Wang	[4] [11] [17] [19] [20] [32]
26	Yanfeng Wang	[37]
27	Yunfeng Wang	[4] [9] [10] [21]
28	Xing Wei	[35]
29	Qiang Wu	[6] [10] [12]
30	Weimin Wu	[3] [5] [7] [16] [18] [26]
31	Yu-Liang Wu (David Yu-Liang Wu)	[2]
32	Hongxi Xue	[1] [3] [6] [12]
33	Hannah Honghua Yang (Honghua Yang)	[13] [15] [24]
34	Hannal Yang	[8]
35	Liu Yang	[10]
36	Xiaoqing Yang	[26]
37	Wenjian Yu	[24]
38	Shan Zeng	[15] [24]
39	Hui Zhang	[28]
40	Jianzhou Zhao	[7]
41	Kang Zhao	[14] [21] [23] [27] [30] [31] [33] [36] [38]
42	Yanni Zhao	[26]
43	Zhen Zhao	[21]
44	Qiang Zhou	[8] [10] [13] [15] [24] [25] [35] [37] [39]
45	Liang Zhu	[19] [22]
46	Ming Zhu	[3] [5]

Colors in the list of coauthors