Helmut E. Graeb

2008
29	EE	David Binkley, Helmut E. Graeb, Georges G. E. Gielen, Jaijeet S. Roychowdhury: From Transistor to PLL - Analogue Design and EDA Methods. DATE 2008
28	EE	Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann: Sizing Rules for Bipolar Analog Circuit Design. DATE 2008: 140-145
27	EE	Michael Pehl, Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann: A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters. ICCD 2008: 188-193
26	EE	Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann: The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2209-2222 (2008)
2007
25	EE	Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann: Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming. DATE 2007: 75-80
24	EE	Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann: Pareto-Front Computation and Automatic Sizing of CPPLLs. ISQED 2007: 481-486
23	EE	Guido Stehr, Helmut E. Graeb, Kurt Antreich: Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1733-1748 (2007)
2006
22	EE	Jun Zou, Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann: A CPPLL hierarchical optimization methodology considering jitter, power and locking time. DAC 2006: 19-24
21	EE	Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann: Fast evaluation of analog circuit structures by polytopal approximations. ISCAS 2006
2005
20	EE	Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann: Deterministic approaches to analog performance space exploration (PSE). DAC 2005: 869-874
19		Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann: Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen. GI Jahrestagung (1) 2005: 334-338
2004
18	EE	Guido Stehr, Helmut E. Graeb, Kurt Antreich: Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing. ICCAD 2004: 847-854
2003
17	EE	Guido Stehr, Helmut E. Graeb, Kurt Antreich: Performance trade-off analysis of analog circuits by normal-boundary intersection. DAC 2003: 958-963
16	EE	Guido Stehr, Michael Pronath, Frank Schenkel, Helmut E. Graeb, Kurt Antreich: Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification. ICCAD 2003: 241-246
2002
15	EE	Robert Schwencker, Frank Schenkel, Michael Pronath, Helmut E. Graeb: Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets. DATE 2002: 581-585
14	EE	Michael Pronath, Helmut E. Graeb, Kurt Antreich: A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits. DATE 2002: 78-83
2001
13	EE	Frank Schenkel, Michael Pronath, Stephan Zizala, Robert Schwencker, Helmut E. Graeb, Kurt Antreich: Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search. DAC 2001: 858-863
12	EE	Helmut E. Graeb, Stephan Zizala, Josef Eckmueller, Kurt Antreich: The Sizing Rules Method for Analog Integrated Circuit Design. ICCAD 2001: 343-349
2000
11	EE	Robert Schwencker, Frank Schenkel, Helmut E. Graeb, Kurt Antreich: The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits. DATE 2000: 42-47
10		Michael Pronath, Volker Gloeckel, Helmut E. Graeb: A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits. ICCAD 2000: 557-561
1999
9	EE	Robert Schwencker, Josef Eckmueller, Helmut E. Graeb, Kurt Antreich: Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints. DATE 1999: 323-327
8	EE	Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich: Analog testing by characteristic observation inference. IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1353-1368 (1999)
1998
7	EE	Josef Eckmueller, Martin Groepl, Helmut E. Graeb: Hierarchical Characterization of Analog Integrated CMOS Circuits. DATE 1998: 636-643
6	EE	Walter M. Lindermeir, Thomas J. Vogels, Helmut E. Graeb: Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults. DATE 1998: 822-
1995
5	EE	Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich: Design based analog testing by Characteristic Observation Inference. ICCAD 1995: 620-626
1994
4	EE	Wolfgang T. Eisenmann, Helmut E. Graeb: Fast transient power and noise estimation for VLSI circuits. ICCAD 1994: 252-257
3	EE	Kurt Antreich, Helmut E. Graeb, Claudia U. Wieser: Circuit analysis and optimization driven by worst-case distances. IEEE Trans. on CAD of Integrated Circuits and Systems 13(1): 57-71 (1994)
1993
2	EE	Helmut E. Graeb, Claudia U. Wieser, Kurt Antreich: Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances. DAC 1993: 142-147
1991
1		Kurt Antreich, Helmut E. Graeb: Circuit Optimization Driven by Worst-Case Distances. ICCAD 1991: 166-169

Coauthor Index

1	Kurt Antreich	[1] [2] [3] [5] [8] [9] [11] [12] [13] [14] [16] [17] [18] [23]
2	David Binkley	[29]
3	Josef Eckmueller	[7] [9] [12]
4	Wolfgang T. Eisenmann	[4]
5	Georges G. E. Gielen	[29]
6	Volker Gloeckel	[10]
7	Martin Groepl	[7]
8	Walter M. Lindermeir	[5] [6] [8]
9	Tobias Massier	[26] [27] [28]
10	Daniel Mueller	[19] [20] [21] [22] [24] [25]
11	Michael Pehl	[27]
12	Michael Pronath	[10] [13] [14] [15] [16]
13	Jaijeet S. Roychowdhury	[29]
14	Frank Schenkel	[11] [13] [15] [16]
15	Ulf Schlichtmann	[19] [20] [21] [22] [24] [25] [26] [27] [28]
16	Robert Schwencker	[9] [11] [13] [15]
17	Guido Stehr	[16] [17] [18] [19] [20] [21] [23]
18	Thomas J. Vogels	[6]
19	Claudia U. Wieser	[2] [3]
20	Stephan Zizala	[12] [13]
21	Jun Zou	[22] [24]

Colors in the list of coauthors