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Soroush Abbaspour

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2008
14EEPeter Feldmann, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta: Driver waveform computation for timing analysis with multiple voltage threshold driver models. DAC 2008: 425-428
13EEPeter Feldmann, Soroush Abbaspour: Towards a more physical approach to gate modeling for timing, noise, and power. DAC 2008: 453-455
12EEDebjit Sinha, Gregory Schaeffer, Soroush Abbaspour, Alex Rubin, Frank Borkam: Constrained aggressor set selection for maximum coupling noise. ICCAD 2008: 790-796
2007
11EESoroush Abbaspour, Hanif Fatemi, Massoud Pedram: Parameterized Non-Gaussian Variational Gate Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1495-1508 (2007)
2006
10EEHanif Fatemi, Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Emre Tuncer: SACI: statistical static timing analysis of coupled interconnects. ACM Great Lakes Symposium on VLSI 2006: 241-246
9EESoroush Abbaspour, Hanif Fatemi, Massoud Pedram: Parameterized block-based non-gaussian statistical gate timing analysis. ASP-DAC 2006: 947-952
8EESoroush Abbaspour, Hanif Fatemi, Massoud Pedram: Non-gaussian statistical interconnect timing analysis. DATE 2006: 533-538
7EESoroush Abbaspour, Massoud Pedram, Amir H. Ajami, Chandramouli V. Kashyap: Fast Interconnect and Gate Timing Analysis for Performance Optimization. IEEE Trans. VLSI Syst. 14(12): 1383-1388 (2006)
2005
6EESoroush Abbaspour, Hanif Fatemi, Massoud Pedram: VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input. ACM Great Lakes Symposium on VLSI 2005: 426-430
5EESoroush Abbaspour, Hanif Fatemi, Massoud Pedram: VGTA: Variation Aware Gate Timing Analysis. ICCD 2005: 351-356
2004
4EESoroush Abbaspour, Amir H. Ajami, Massoud Pedram, Emre Tuncer: TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnects. ACM Great Lakes Symposium on VLSI 2004: 19-24
3EESoroush Abbaspour, Massoud Pedram: Gate delay calculation considering the crosstalk capacitances. ASP-DAC 2004: 852-857
2003
2EEChang Woo Kang, Soroush Abbaspour, Massoud Pedram: Buffer sizing for minimum energy-delay product by using an approximating polynomial. ACM Great Lakes Symposium on VLSI 2003: 112-115
1EESoroush Abbaspour, Massoud Pedram, Payam Heydari: Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers. ISQED 2003: 261-266

Coauthor Index

1Amir H. Ajami [4] [7] [10]
2Revanta Banerji [14]
3Frank Borkam [12]
4Hanif Fatemi [5] [6] [8] [9] [10] [11]
5Peter Feldmann [13] [14]
6Hemlata Gupta [14]
7Payam Heydari [1]
8Chang Woo Kang [2]
9Chandramouli V. Kashyap [7]
10Massoud Pedram [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
11Alex Rubin [12]
12Gregory Schaeffer [12] [14]
13Debjit Sinha [12] [14]
14Emre Tuncer [4] [10]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)