2008 |
21 | EE | Oliver Wienand,
Markus Wedler,
Dominik Stoffel,
Wolfgang Kunz,
Gert-Martin Greuel:
An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths.
CAV 2008: 473-486 |
20 | EE | Evgeny Pavlenko,
Markus Wedler,
Dominik Stoffel,
Wolfgang Kunz,
Oliver Wienand,
Evgeny Karibaev:
Modeling of Custom-Designed Arithmetic Components for ABL Normalization.
FDL 2008: 124-129 |
19 | EE | Minh D. Nguyen,
Max Thalmaier,
Markus Wedler,
J. Bormann,
Dominik Stoffel,
Wolfgang Kunz:
Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2068-2082 (2008) |
2007 |
18 | EE | Markus Wedler,
Dominik Stoffel,
Raik Brinkmann,
Wolfgang Kunz:
A Normalization Method for Arithmetic Data-Path Verification.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1909-1922 (2007) |
2005 |
17 | EE | Markus Wedler,
Dominik Stoffel,
Wolfgang Kunz:
Normalization at the arithmetic bit level.
DAC 2005: 457-462 |
16 | | Minh D. Nguyen,
Dominik Stoffel,
Wolfgang Kunz:
Enhancing BMC-based Protocol Verification Using Transition-By-Transition FSM Traversal.
GI Jahrestagung (1) 2005: 303-307 |
15 | | Minh D. Nguyen,
Dominik Stoffel,
Markus Wedler,
Wolfgang Kunz:
Transition-by-transition FSM traversal for reachability analysis in bounded model checking.
ICCAD 2005: 1068-1075 |
2004 |
14 | EE | Markus Wedler,
Dominik Stoffel,
Wolfgang Kunz:
Exploiting state encoding for invariant generation in induction-based property checking.
ASP-DAC 2004: 424-429 |
13 | EE | Klaus Winkelmann,
Hans-Joachim Trylus,
Dominik Stoffel,
Görschwin Fey:
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor.
DATE 2004: 162-167 |
12 | EE | Markus Wedler,
Dominik Stoffel,
Wolfgang Kunz:
Arithmetic Reasoning in DPLL-Based SAT Solving.
DATE 2004: 30-35 |
11 | EE | Ingmar Neumann,
Dominik Stoffel,
Kolja Sulimma,
Michel R. C. M. Berkelaar,
Wolfgang Kunz:
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning.
ICCD 2004: 350-353 |
10 | EE | Dominik Stoffel,
Wolfgang Kunz:
Equivalence checking of arithmetic circuits on the arithmetic bit level.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 586-597 (2004) |
9 | EE | Dominik Stoffel,
Markus Wedler,
Peter Warkentin,
Wolfgang Kunz:
Structural FSM traversal.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 598-619 (2004) |
2003 |
8 | EE | Markus Wedler,
Dominik Stoffel,
Wolfgang Kunz:
Using RTL Statespace Information and State Encoding for Induction Based Property Checking.
DATE 2003: 11156-11157 |
2002 |
7 | EE | Markus Wedler,
Dominik Stoffel,
Wolfgang Kunz:
Improving Structural FSM Traversal by Constraint-Satisfying Logic Simulation.
ISVLSI 2002: 151-158 |
2001 |
6 | EE | Dominik Stoffel,
Wolfgang Kunz:
Verification of Integer Multipliers on the Arithmetic Bit Level.
ICCAD 2001: 183-189 |
5 | EE | Hendrik Hartje,
Ingmar Neumann,
Dominik Stoffel,
Wolfgang Kunz:
Cycle time optimization by timing driven placement with simultaneous netlist transformations.
ISCAS (5) 2001: 359-362 |
1999 |
4 | | Kolja Sulimma,
Dominik Stoffel,
Wolfgang Kunz:
Accelerating Boolean Implications with FPGAs.
FPL 1999: 532-537 |
3 | EE | Ingmar Neumann,
Dominik Stoffel,
Hendrik Hartje,
Wolfgang Kunz:
Cell replication and redundancy elimination during placement for cycle time optimization.
ICCAD 1999: 25-30 |
1997 |
2 | EE | Dominik Stoffel,
Wolfgang Kunz:
Record & play: a structural fixed point iteration for sequential circuit verification.
ICCAD 1997: 394-399 |
1 | EE | Wolfgang Kunz,
Dominik Stoffel,
Premachandran R. Menon:
Logic optimization and equivalence checking by implication analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 266-281 (1997) |