Kirill Minkovich

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2008

4 EE Kirill Minkovich, Jason Cong: Mapping for better than worst-case delays in LUT-based FPGA designs. FPGA 2008: 56-64

2007

3 EE Jason Cong, Kirill Minkovich: Improved SAT-based Boolean matching using implicants for LUT-based FPGAs. FPGA 2007: 139-147

2 EE Jason Cong, Kirill Minkovich: Optimality Study of Logic Synthesis for LUT-Based FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 230-239 (2007)

2006

1 EE Jason Cong, Kirill Minkovich: Optimality study of logic synthesis for LUT-based FPGAs. FPGA 2006: 33-40

2008
4	EE	Kirill Minkovich, Jason Cong: Mapping for better than worst-case delays in LUT-based FPGA designs. FPGA 2008: 56-64
2007
3	EE	Jason Cong, Kirill Minkovich: Improved SAT-based Boolean matching using implicants for LUT-based FPGAs. FPGA 2007: 139-147
2	EE	Jason Cong, Kirill Minkovich: Optimality Study of Logic Synthesis for LUT-Based FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 230-239 (2007)
2006
1	EE	Jason Cong, Kirill Minkovich: Optimality study of logic synthesis for LUT-based FPGAs. FPGA 2006: 33-40

Coauthor Index

1 Jason Cong [1] [2] [3] [4]